Lines Matching defs:out
518 Location out = locations->Out(); in EmitNativeCode() local
724 Location out, in ReadBarrierForHeapReferenceSlowPathARMVIXL()
910 ReadBarrierForRootSlowPathARMVIXL(HInstruction* instruction, Location out, Location root) in ReadBarrierForRootSlowPathARMVIXL()
1065 vixl32::Register out, in GenerateDataProcInstruction()
1100 const Location& out, in GenerateDataProc()
1136 const Location out = locations->Out(); in GenerateLongDataProc() local
1527 const vixl32::Register out = OutputRegister(cond); in GenerateConditionGeneric() local
1558 const vixl32::Register out = OutputRegister(cond); in GenerateEqualLong() local
1614 const vixl32::Register out = OutputRegister(cond); in GenerateConditionLong() local
1686 const vixl32::Register out = OutputRegister(cond); in GenerateConditionIntegralOrNonPrimitive() local
1791 static bool CanGenerateConditionalMove(const Location& out, const Location& src) { in CanGenerateConditionalMove()
2864 const Location out = locations->Out(); in VisitSelect() local
3021 vixl32::Register out, in GenerateConditionWithZero()
3133 const vixl32::Register out = OutputRegister(cond); in HandleCondition() local
3587 Location out = locations->Out(); in VisitNeg() local
3772 Location out = locations->Out(); in VisitTypeConversion() local
4028 Location out = locations->Out(); in VisitAdd() local
4091 Location out = locations->Out(); in VisitSub() local
4149 Location out = locations->Out(); in VisitMul() local
4207 vixl32::Register out = OutputRegister(instruction); in DivRemOneOrMinusOne() local
4231 vixl32::Register out = OutputRegister(instruction); in DivRemByPowerOfTwo() local
4237 auto generate_div_code = [this, imm, ctz_imm](vixl32::Register out, vixl32::Register in) { in DivRemByPowerOfTwo()
4311 vixl32::Register out = OutputRegister(instruction); in GenerateDivRemWithAnyConstant() local
4324 vixl32::Register temp2) { in GenerateDivRemWithAnyConstant()
4695 vixl32::Register out = RegisterFrom(out_loc); in GenerateMinMaxInt() local
4763 vixl32::SRegister out = SRegisterFrom(out_loc); in GenerateMinMaxFloat() local
4824 vixl32::DRegister out = DRegisterFrom(out_loc); in GenerateMinMaxDouble() local
5006 vixl32::Register out = OutputRegister(ror); in HandleIntegerRotate() local
5183 Location out = locations->Out(); in HandleShift() local
5445 Location out = locations->Out(); in VisitNot() local
5504 vixl32::Register out = OutputRegister(compare); in VisitCompare() local
5941 Location out = locations->Out(); in HandleFieldGet() local
6431 vixl32::Register out = OutputRegister(instruction); in VisitArrayGet() local
6499 vixl32::SRegister out = SRegisterFrom(out_loc); in VisitArrayGet() local
6834 vixl32::Register out = OutputRegister(instruction); in VisitArrayLength() local
6858 vixl32::Register out = OutputRegister(instruction); in VisitIntermediateAddress() local
7359 vixl32::Register out = OutputRegister(cls); in VisitLoadClass() local
7599 vixl32::Register out = OutputRegister(load); in VisitLoadString() local
7673 vixl32::Register out = OutputRegister(load); in VisitLoadException() local
7774 vixl32::Register out = OutputRegister(instruction); in VisitInstanceOf() local
8342 Location out = locations->Out(); in VisitBitwiseNegatedRight() local
8468 void InstructionCodeGeneratorARMVIXL::GenerateAndConst(vixl32::Register out, in GenerateAndConst()
8493 void InstructionCodeGeneratorARMVIXL::GenerateOrrConst(vixl32::Register out, in GenerateOrrConst()
8516 void InstructionCodeGeneratorARMVIXL::GenerateEorConst(vixl32::Register out, in GenerateEorConst()
8529 void InstructionCodeGeneratorARMVIXL::GenerateAddLongConst(Location out, in GenerateAddLongConst()
8558 Location out = locations->Out(); in HandleBitwiseOperation() local
8632 Location out, in GenerateReferenceLoadOneRegister()
8665 Location out, in GenerateReferenceLoadTwoRegisters()
8966 Location out, in GenerateReadBarrierSlow()
8993 Location out, in MaybeGenerateReadBarrierSlow()
9011 Location out, in GenerateReadBarrierForRootSlow()
9720 vixl32::Register out) { in EmitMovwMovtPlaceholder()