56 using helpers::InputRegisterAt;
1519     __ Cmp(InputRegisterAt(condition, 0), InputOperandAt(condition, 1));  in GenerateTest()
1685   vixl32::Register in = InputRegisterAt(cond, 0);  in GenerateConditionIntegralOrNonPrimitive()
2727       __ CompareAndBranchIfZero(InputRegisterAt(instruction, condition_input_index),  in GenerateTestAndBranch()
2731       __ CompareAndBranchIfNonZero(InputRegisterAt(instruction, condition_input_index),  in GenerateTestAndBranch()
2750     const vixl32::Register left = InputRegisterAt(cond, 0);  in GenerateTestAndBranch()
2918         __ Cmp(InputRegisterAt(select, 2), 0);  in VisitSelect()
3132     vixl32::Register left = InputRegisterAt(cond, 0);  in HandleCondition()
3591       __ Rsb(OutputRegister(neg), InputRegisterAt(neg, 0), 0);  in VisitNeg()
3785           __ Ubfx(OutputRegister(conversion), InputRegisterAt(conversion, 0), 0, 8);  in VisitTypeConversion()
3803           __ Sbfx(OutputRegister(conversion), InputRegisterAt(conversion, 0), 0, 8);  in VisitTypeConversion()
3820           __ Ubfx(OutputRegister(conversion), InputRegisterAt(conversion, 0), 0, 16);  in VisitTypeConversion()
3836           __ Sbfx(OutputRegister(conversion), InputRegisterAt(conversion, 0), 0, 16);  in VisitTypeConversion()
3897           __ Mov(LowRegisterFrom(out), InputRegisterAt(conversion, 0));  in VisitTypeConversion()
3926           __ Vmov(OutputSRegister(conversion), InputRegisterAt(conversion, 0));  in VisitTypeConversion()
3953           __ Vmov(LowSRegisterFrom(out), InputRegisterAt(conversion, 0));  in VisitTypeConversion()
4034       __ Add(OutputRegister(add), InputRegisterAt(add, 0), InputOperandAt(add, 1));  in VisitAdd()
4096       __ Sub(OutputRegister(sub), InputRegisterAt(sub, 0), InputOperandAt(sub, 1));  in VisitSub()
4154       __ Mul(OutputRegister(mul), InputRegisterAt(mul, 0), InputRegisterAt(mul, 1));  in VisitMul()
4208   vixl32::Register dividend = InputRegisterAt(instruction, 0);  in DivRemOneOrMinusOne()
4232   vixl32::Register dividend = InputRegisterAt(instruction, 0);  in DivRemByPowerOfTwo()
4312   vixl32::Register dividend = InputRegisterAt(instruction, 0);  in GenerateDivRemWithAnyConstant()
4488         __ Sdiv(OutputRegister(div), InputRegisterAt(div, 0), InputRegisterAt(div, 1));  in VisitDiv()
4612         vixl32::Register reg1 = InputRegisterAt(rem, 0);  in VisitRem()
4974         __ CompareAndBranchIfZero(InputRegisterAt(instruction, 0), slow_path->GetEntryLabel());  in VisitDivZeroCheck()
5004   vixl32::Register in = InputRegisterAt(ror, 0);  in HandleIntegerRotate()
5191       vixl32::Register first_reg = InputRegisterAt(op, 0);  in HandleShift()
5449       __ Mvn(OutputRegister(not_), InputRegisterAt(not_, 0));  in VisitNot()
5689   vixl32::Register base = InputRegisterAt(instruction, 0);  in HandleFieldSet()
5940   vixl32::Register base = InputRegisterAt(instruction, 0);  in HandleFieldGet()
6170   __ ldr(temps.Acquire(), MemOperand(InputRegisterAt(instruction, 0)));  in GenerateImplicitNullCheck()
6178   __ CompareAndBranchIfZero(InputRegisterAt(instruction, 0), slow_path->GetEntryLabel());  in GenerateExplicitNullCheck()
6302   vixl32::Register obj = InputRegisterAt(instruction, 0);  in VisitArrayGet()
6565   vixl32::Register array = InputRegisterAt(instruction, 0);  in VisitArraySet()
6833   vixl32::Register obj = InputRegisterAt(instruction, 0);  in VisitArrayLength()
6859   vixl32::Register first = InputRegisterAt(instruction, 0);  in VisitIntermediateAddress()
7370       vixl32::Register current_method = InputRegisterAt(cls, 0);  in VisitLoadClass()
7478   GenerateClassInitializationCheck(slow_path, InputRegisterAt(check, 0));  in VisitClinitCheck()
7769   vixl32::Register obj = InputRegisterAt(instruction, 0);  in VisitInstanceOf()
7772       : InputRegisterAt(instruction, 1);  in VisitInstanceOf()
8063   vixl32::Register obj = InputRegisterAt(instruction, 0);  in VisitCheckCast()
8066       : InputRegisterAt(instruction, 1);  in VisitCheckCast()
8413     const vixl32::Register first = InputRegisterAt(instruction, 0);  in VisitDataProcWithShifterOp()
8417         : InputRegisterAt(instruction, 1);  in VisitDataProcWithShifterOp()
8452       const vixl32::Register second = InputRegisterAt(instruction, 1);  in VisitDataProcWithShifterOp()
8564       vixl32::Register first_reg = InputRegisterAt(instruction, 0);  in HandleBitwiseOperation()
8597     vixl32::Register first_reg = InputRegisterAt(instruction, 0);  in HandleBitwiseOperation()
8598     vixl32::Register second_reg = InputRegisterAt(instruction, 1);  in HandleBitwiseOperation()
9516       InputRegisterAt(instr, HMultiplyAccumulate::kInputAccumulatorIndex);  in VisitMultiplyAccumulate()
9518       InputRegisterAt(instr, HMultiplyAccumulate::kInputMulLeftIndex);  in VisitMultiplyAccumulate()
9520       InputRegisterAt(instr, HMultiplyAccumulate::kInputMulRightIndex);  in VisitMultiplyAccumulate()
9558   vixl32::Register value_reg = InputRegisterAt(switch_instr, 0);  in VisitPackedSwitch()
9675                                    InputRegisterAt(instruction, 0),  in VisitClassTableGet()
9682                                    InputRegisterAt(instruction, 0),  in VisitClassTableGet()