Lines Matching refs:dst
56 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReplicateScalar() local
62 __ Vdup(Untyped8, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
67 __ Vdup(Untyped16, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
71 __ Vdup(Untyped32, dst, InputRegisterAt(instruction, 0)); in VisitVecReplicateScalar()
137 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecReduce() local
143 __ Vpadd(DataTypeValue::I32, dst, src, src); in VisitVecReduce()
146 __ Vpmin(DataTypeValue::S32, dst, src, src); in VisitVecReduce()
149 __ Vpmax(DataTypeValue::S32, dst, src, src); in VisitVecReduce()
174 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNeg() local
179 __ Vneg(DataTypeValue::S8, dst, src); in VisitVecNeg()
184 __ Vneg(DataTypeValue::S16, dst, src); in VisitVecNeg()
188 __ Vneg(DataTypeValue::S32, dst, src); in VisitVecNeg()
203 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAbs() local
207 __ Vabs(DataTypeValue::S8, dst, src); in VisitVecAbs()
211 __ Vabs(DataTypeValue::S16, dst, src); in VisitVecAbs()
215 __ Vabs(DataTypeValue::S32, dst, src); in VisitVecAbs()
230 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecNot() local
234 __ Vmov(I8, dst, 1); in VisitVecNot()
235 __ Veor(dst, dst, src); in VisitVecNot()
242 __ Vmvn(I8, dst, src); // lanes do not matter in VisitVecNot()
278 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAdd() local
283 __ Vadd(I8, dst, lhs, rhs); in VisitVecAdd()
288 __ Vadd(I16, dst, lhs, rhs); in VisitVecAdd()
292 __ Vadd(I32, dst, lhs, rhs); in VisitVecAdd()
308 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSaturationAdd() local
312 __ Vqadd(DataTypeValue::U8, dst, lhs, rhs); in VisitVecSaturationAdd()
316 __ Vqadd(DataTypeValue::S8, dst, lhs, rhs); in VisitVecSaturationAdd()
320 __ Vqadd(DataTypeValue::U16, dst, lhs, rhs); in VisitVecSaturationAdd()
324 __ Vqadd(DataTypeValue::S16, dst, lhs, rhs); in VisitVecSaturationAdd()
340 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecHalvingAdd() local
345 ? __ Vrhadd(DataTypeValue::U8, dst, lhs, rhs) in VisitVecHalvingAdd()
346 : __ Vhadd(DataTypeValue::U8, dst, lhs, rhs); in VisitVecHalvingAdd()
351 ? __ Vrhadd(DataTypeValue::S8, dst, lhs, rhs) in VisitVecHalvingAdd()
352 : __ Vhadd(DataTypeValue::S8, dst, lhs, rhs); in VisitVecHalvingAdd()
357 ? __ Vrhadd(DataTypeValue::U16, dst, lhs, rhs) in VisitVecHalvingAdd()
358 : __ Vhadd(DataTypeValue::U16, dst, lhs, rhs); in VisitVecHalvingAdd()
363 ? __ Vrhadd(DataTypeValue::S16, dst, lhs, rhs) in VisitVecHalvingAdd()
364 : __ Vhadd(DataTypeValue::S16, dst, lhs, rhs); in VisitVecHalvingAdd()
380 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSub() local
385 __ Vsub(I8, dst, lhs, rhs); in VisitVecSub()
390 __ Vsub(I16, dst, lhs, rhs); in VisitVecSub()
394 __ Vsub(I32, dst, lhs, rhs); in VisitVecSub()
410 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSaturationSub() local
414 __ Vqsub(DataTypeValue::U8, dst, lhs, rhs); in VisitVecSaturationSub()
418 __ Vqsub(DataTypeValue::S8, dst, lhs, rhs); in VisitVecSaturationSub()
422 __ Vqsub(DataTypeValue::U16, dst, lhs, rhs); in VisitVecSaturationSub()
426 __ Vqsub(DataTypeValue::S16, dst, lhs, rhs); in VisitVecSaturationSub()
442 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecMul() local
447 __ Vmul(I8, dst, lhs, rhs); in VisitVecMul()
452 __ Vmul(I16, dst, lhs, rhs); in VisitVecMul()
456 __ Vmul(I32, dst, lhs, rhs); in VisitVecMul()
480 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecMin() local
484 __ Vmin(DataTypeValue::U8, dst, lhs, rhs); in VisitVecMin()
488 __ Vmin(DataTypeValue::S8, dst, lhs, rhs); in VisitVecMin()
492 __ Vmin(DataTypeValue::U16, dst, lhs, rhs); in VisitVecMin()
496 __ Vmin(DataTypeValue::S16, dst, lhs, rhs); in VisitVecMin()
500 __ Vmin(DataTypeValue::U32, dst, lhs, rhs); in VisitVecMin()
504 __ Vmin(DataTypeValue::S32, dst, lhs, rhs); in VisitVecMin()
520 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecMax() local
524 __ Vmax(DataTypeValue::U8, dst, lhs, rhs); in VisitVecMax()
528 __ Vmax(DataTypeValue::S8, dst, lhs, rhs); in VisitVecMax()
532 __ Vmax(DataTypeValue::U16, dst, lhs, rhs); in VisitVecMax()
536 __ Vmax(DataTypeValue::S16, dst, lhs, rhs); in VisitVecMax()
540 __ Vmax(DataTypeValue::U32, dst, lhs, rhs); in VisitVecMax()
544 __ Vmax(DataTypeValue::S32, dst, lhs, rhs); in VisitVecMax()
561 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecAnd() local
569 __ Vand(I8, dst, lhs, rhs); in VisitVecAnd()
593 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecOr() local
601 __ Vorr(I8, dst, lhs, rhs); in VisitVecOr()
617 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecXor() local
625 __ Veor(I8, dst, lhs, rhs); in VisitVecXor()
659 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecShl() local
665 __ Vshl(I8, dst, lhs, value); in VisitVecShl()
670 __ Vshl(I16, dst, lhs, value); in VisitVecShl()
674 __ Vshl(I32, dst, lhs, value); in VisitVecShl()
689 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecShr() local
695 __ Vshr(DataTypeValue::S8, dst, lhs, value); in VisitVecShr()
700 __ Vshr(DataTypeValue::S16, dst, lhs, value); in VisitVecShr()
704 __ Vshr(DataTypeValue::S32, dst, lhs, value); in VisitVecShr()
719 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecUShr() local
725 __ Vshr(DataTypeValue::U8, dst, lhs, value); in VisitVecUShr()
730 __ Vshr(DataTypeValue::U16, dst, lhs, value); in VisitVecUShr()
734 __ Vshr(DataTypeValue::U32, dst, lhs, value); in VisitVecUShr()
764 vixl32::DRegister dst = DRegisterFrom(locations->Out()); in VisitVecSetScalars() local
769 __ Vmov(I32, dst, 0); in VisitVecSetScalars()
780 __ Vmov(Untyped32, DRegisterLane(dst, 0), InputRegisterAt(instruction, 0)); in VisitVecSetScalars()