95     if (reg.AsArm().IsCoreRegister()) {  in BuildFrame()
96       core_spill_mask |= 1 << reg.AsArm().AsCoreRegister();  in BuildFrame()
98       fp_spill_mask |= 1 << reg.AsArm().AsSRegister();  in BuildFrame()
125     CHECK(r0.Is(AsVIXLRegister(method_reg.AsArm())));  in BuildFrame()
140     if (reg.AsArm().IsCoreRegister()) {  in RemoveFrame()
141       core_spill_mask |= 1u << reg.AsArm().AsCoreRegister();  in RemoveFrame()
143       fp_spill_mask |= 1u << reg.AsArm().AsSRegister();  in RemoveFrame()
219   ArmManagedRegister src = m_src.AsArm();  in Store()
243   vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm());  in StoreRef()
250   vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm());  in StoreRawPtr()
259   vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm());  in StoreSpanning()
280   asm_.LoadFromOffset(kLoadWord, scratch, AsVIXLRegister(base.AsArm()), offs.Int32Value());  in CopyRef()
291   vixl::aarch32::Register dest = AsVIXLRegister(mdest.AsArm());  in LoadRef()
292   vixl::aarch32::Register base = AsVIXLRegister(mbase.AsArm());  in LoadRef()
321   return Load(m_dst.AsArm(), sp, src.Int32Value(), size);  in Load()
327   return Load(m_dst.AsArm(), tr, src.Int32Value(), size);  in LoadFromThread()
331   vixl::aarch32::Register dest = AsVIXLRegister(mdest.AsArm());  in LoadRawPtrFromThread()
419   ArmManagedRegister first_src_reg = first_src.GetRegister().AsArm();  in GetSpillChunkSize()
425            IsCoreRegisterOrPair(srcs[end].GetRegister().AsArm())) {  in GetSpillChunkSize()
434            !IsCoreRegisterOrPair(srcs[end].GetRegister().AsArm()) &&  in GetSpillChunkSize()
435            GetSRegisterNumber(srcs[end].GetRegister().AsArm()) == next_sreg) {  in GetSpillChunkSize()
458     mask |= GetCoreRegisterMask(loc.GetRegister().AsArm());  in GetCoreRegisterMask()
471          srcs[start].GetRegister().AsArm().IsCoreRegister() &&  in UseStrdForChunk()
472          srcs[start + 1u].GetRegister().AsArm().IsCoreRegister();  in UseStrdForChunk()
482          srcs[start].GetRegister().AsArm().IsSRegister() &&  in UseVstrForChunk()
483          srcs[start + 1u].GetRegister().AsArm().IsSRegister() &&  in UseVstrForChunk()
484          IsAligned<2u>(static_cast<size_t>(srcs[start].GetRegister().AsArm().AsSRegister()));  in UseVstrForChunk()
510     DCHECK(dest.IsRegister() && IsCoreRegisterOrPair(dest.GetRegister().AsArm()));  in MoveArguments()
511     if (src.IsRegister() && IsCoreRegisterOrPair(src.GetRegister().AsArm())) {  in MoveArguments()
515       src_regs |= GetCoreRegisterMask(src.GetRegister().AsArm());  in MoveArguments()
517     dest_regs |= GetCoreRegisterMask(dest.GetRegister().AsArm());  in MoveArguments()
559         ___ Strd(AsVIXLRegister(srcs[i].GetRegister().AsArm()),  in MoveArguments()
560                  AsVIXLRegister(srcs[i + 1u].GetRegister().AsArm()),  in MoveArguments()
563         size_t sreg = GetSRegisterNumber(src.GetRegister().AsArm());  in MoveArguments()
576         ArmManagedRegister src_reg = src.GetRegister().AsArm();  in MoveArguments()
607       DCHECK(dests[i].IsRegister() && IsCoreRegisterOrPair(dests[i].GetRegister().AsArm()));  in MoveArguments()
608       if (!srcs[i].IsRegister() || !IsCoreRegisterOrPair(srcs[i].GetRegister().AsArm())) {  in MoveArguments()
611       uint32_t dest_reg_mask = GetCoreRegisterMask(dests[i].GetRegister().AsArm());  in MoveArguments()
621       uint32_t src_reg_mask = GetCoreRegisterMask(srcs[i].GetRegister().AsArm());  in MoveArguments()
634     DCHECK(dests[i].IsRegister() && IsCoreRegisterOrPair(dests[i].GetRegister().AsArm()));  in MoveArguments()
635     if (srcs[i].IsRegister() && IsCoreRegisterOrPair(srcs[i].GetRegister().AsArm())) {  in MoveArguments()
636       DCHECK_EQ(GetCoreRegisterMask(dests[i].GetRegister().AsArm()) & dest_regs, 0u);  in MoveArguments()
639     DCHECK_NE(GetCoreRegisterMask(dests[i].GetRegister().AsArm()) & dest_regs, 0u);  in MoveArguments()
643              (srcs[j].IsRegister() && IsCoreRegisterOrPair(srcs[j].GetRegister().AsArm()))) {  in MoveArguments()
644         DCHECK_EQ(GetCoreRegisterMask(dests[j].GetRegister().AsArm()) & dest_regs, 0u);  in MoveArguments()
649           ___ Ldrd(AsVIXLRegister(dests[i].GetRegister().AsArm()),  in MoveArguments()
650                    AsVIXLRegister(dests[j].GetRegister().AsArm()),  in MoveArguments()
656           uint32_t first_sreg = GetSRegisterNumber(srcs[i].GetRegister().AsArm());  in MoveArguments()
658               first_sreg + 1u == GetSRegisterNumber(srcs[j].GetRegister().AsArm())) {  in MoveArguments()
659             ___ Vmov(AsVIXLRegister(dests[i].GetRegister().AsArm()),  in MoveArguments()
660                      AsVIXLRegister(dests[j].GetRegister().AsArm()),  in MoveArguments()
679   ArmManagedRegister dst = mdst.AsArm();  in Move()
695   ArmManagedRegister src = msrc.AsArm();  in Move()
800   vixl::aarch32::Register out_reg = AsVIXLRegister(mout_reg.AsArm());  in CreateHandleScopeEntry()
802       min_reg.AsArm().IsNoRegister() ? vixl::aarch32::Register() : AsVIXLRegister(min_reg.AsArm());  in CreateHandleScopeEntry()
886   vixl::aarch32::Register base = AsVIXLRegister(mbase.AsArm());  in Jump()
894   vixl::aarch32::Register base = AsVIXLRegister(mbase.AsArm());  in Call()
914   temps.Exclude(AsVIXLRegister(dest.AsArm()));  in GetCurrentThread()
915   ___ Mov(AsVIXLRegister(dest.AsArm()), tr);  in GetCurrentThread()
945   ___ B(ArmVIXLJNIMacroLabel::Cast(label)->AsArm());  in Jump()
957       ___ CompareAndBranchIfZero(scratch, ArmVIXLJNIMacroLabel::Cast(label)->AsArm());  in TestGcMarking()
960       ___ CompareAndBranchIfNonZero(scratch, ArmVIXLJNIMacroLabel::Cast(label)->AsArm());  in TestGcMarking()
970   ___ Bind(ArmVIXLJNIMacroLabel::Cast(label)->AsArm());  in Bind()