Lines Matching refs:r1
22 GET_VREG r1, r3 @ r1<- vCC
25 cmp r1, #0 @ is second operand zero?
55 GET_VREG r1, r3 @ r1<- vB
58 cmp r1, #0 @ is second operand zero?
84 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
89 cmp r1, #0 @ is second operand zero?
123 $extract @ optional; typically r1<- ssssssCC (sign extended)
125 @cmp r1, #0 @ is second operand zero?
160 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
191 mov r1, rINST, lsr #12 @ r1<- B
193 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B]
195 GET_VREG_WIDE_BY_ADDR r2, r3, r1 @ r2/r3<- vBB/vBB+1
196 GET_VREG_WIDE_BY_ADDR r0, r1, r9 @ r0/r1<- vAA/vAA+1
246 GET_VREG_WIDE_BY_ADDR r0, r1, r3 @ r0/r1<- vB/vB+1
268 GET_VREG_WIDE_BY_ADDR r0, r1, r3 @ r0/r1<- vAA
272 $instr @ r0/r1<- op, r2-r3 changed
274 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA<- r0/r1
296 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vA/vA+1<- r0/r1
348 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
351 sbcs ip, r1, r3 @ Sets correct CCs for checking LT (but not EQ/NE)
376 GET_VREG r1, r3 @ r1<- vCC
378 cmp r1, #0 @ is second operand zero?
383 sdiv r0, r0, r1 @ r0<- op
405 GET_VREG r1, r3 @ r1<- vB
407 cmp r1, #0 @ is second operand zero?
412 sdiv r0, r0, r1 @ r0<- op
433 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
437 cmp r1, #0 @ is second operand zero?
442 sdiv r0, r0, r1 @ r0<- op
466 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
467 @cmp r1, #0 @ is second operand zero?
472 sdiv r0, r0, r1 @ r0<- op
544 GET_VREG_WIDE_BY_ADDR r0, r1, r2 @ r0/r1<- vBB/vBB+1
546 mul ip, r2, r1 @ ip<- ZxW
547 umull r1, lr, r2, r0 @ r1/lr <- ZxX
555 SET_VREG_WIDE_BY_ADDR r1, r2 , r0 @ vAA/vAA+1<- r1/r2
568 mov r1, rINST, lsr #12 @ r1<- B
570 VREG_INDEX_TO_ADDR r1, r1 @ r1<- &fp[B]
572 GET_VREG_WIDE_BY_ADDR r2, r3, r1 @ r2/r3<- vBB/vBB+1
573 GET_VREG_WIDE_BY_ADDR r0, r1, rINST @ r0/r1<- vAA/vAA+1
574 mul ip, r2, r1 @ ip<- ZxW
575 umull r1, lr, r2, r0 @ r1/lr <- ZxX
581 SET_VREG_WIDE_BY_ADDR r1, r2, r0 @ vAA/vAA+1<- r1/r2
631 GET_VREG r1, r3 @ r1<- vCC
633 cmp r1, #0 @ is second operand zero?
638 sdiv r2, r0, r1
639 mls r1, r1, r2, r0 @ r1<- op, r0-r2 changed
641 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
644 SET_VREG r1, r9 @ vAA<- r1
663 GET_VREG r1, r3 @ r1<- vB
665 cmp r1, #0 @ is second operand zero?
670 sdiv r2, r0, r1
671 mls r1, r1, r2, r0 @ r1<- op
673 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
676 SET_VREG r1, r9 @ vAA<- r1
694 FETCH_S r1, 1 @ r1<- ssssCCCC (sign-extended)
698 cmp r1, #0 @ is second operand zero?
703 sdiv r2, r0, r1
704 mls r1, r1, r2, r0 @ r1<- op
706 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
709 SET_VREG r1, r9 @ vAA<- r1
730 movs r1, r3, asr #8 @ r1<- ssssssCC (sign extended)
731 @cmp r1, #0 @ is second operand zero?
736 sdiv r2, r0, r1
737 mls r1, r1, r2, r0 @ r1<- op
739 bl __aeabi_idivmod @ r1<- op, r0-r3 changed
742 SET_VREG r1, r9 @ vAA<- r1
784 GET_VREG_WIDE_BY_ADDR r0, r1, r3 @ r0/r1<- vBB/vBB+1
788 mov r1, r1, asl r2 @ r1<- r1 << r2
790 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
792 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
796 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA/vAA+1<- r0/r1
811 GET_VREG_WIDE_BY_ADDR r0, r1, r9 @ r0/r1<- vAA/vAA+1
812 mov r1, r1, asl r2 @ r1<- r1 << r2
814 orr r1, r1, r0, lsr r3 @ r1<- r1 | (r0 << (32-r2))
817 movpl r1, r0, asl ip @ if r2 >= 32, r1<- r0 << (r2-32)
820 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA/vAA+1<- r0/r1
846 GET_VREG_WIDE_BY_ADDR r0, r1, r3 @ r0/r1<- vBB/vBB+1
852 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
854 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
856 mov r1, r1, asr r2 @ r1<- r1 >> r2
858 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA/vAA+1<- r0/r1
873 GET_VREG_WIDE_BY_ADDR r0, r1, r9 @ r0/r1<- vAA/vAA+1
876 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
879 movpl r0, r1, asr ip @ if r2 >= 32, r0<-r1 >> (r2-32)
880 mov r1, r1, asr r2 @ r1<- r1 >> r2
882 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA/vAA+1<- r0/r1
920 GET_VREG_WIDE_BY_ADDR r0, r1, r3 @ r0/r1<- vBB/vBB+1
926 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
928 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
930 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
932 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA/vAA+1<- r0/r1
947 GET_VREG_WIDE_BY_ADDR r0, r1, r9 @ r0/r1<- vAA/vAA+1
950 orr r0, r0, r1, asl r3 @ r0<- r0 | (r1 << (32-r2))
953 movpl r0, r1, lsr ip @ if r2 >= 32, r0<-r1 >>> (r2-32)
954 mov r1, r1, lsr r2 @ r1<- r1 >>> r2
956 SET_VREG_WIDE_BY_ADDR r0, r1, r9 @ vAA/vAA+1<- r0/r1