1 /*
2 * Copyright (C) 2015 The Android Open Source Project
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #ifndef ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_
18 #define ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_
19
20 #include "nodes.h"
21
22 namespace art {
23
24 namespace helpers {
25
CanFitInShifterOperand(HInstruction * instruction)26 inline bool CanFitInShifterOperand(HInstruction* instruction) {
27 if (instruction->IsTypeConversion()) {
28 HTypeConversion* conversion = instruction->AsTypeConversion();
29 DataType::Type result_type = conversion->GetResultType();
30 DataType::Type input_type = conversion->GetInputType();
31 // We don't expect to see the same type as input and result.
32 return DataType::IsIntegralType(result_type) && DataType::IsIntegralType(input_type) &&
33 (result_type != input_type);
34 } else {
35 return (instruction->IsShl() && instruction->AsShl()->InputAt(1)->IsIntConstant()) ||
36 (instruction->IsShr() && instruction->AsShr()->InputAt(1)->IsIntConstant()) ||
37 (instruction->IsUShr() && instruction->AsUShr()->InputAt(1)->IsIntConstant());
38 }
39 }
40
HasShifterOperand(HInstruction * instr,InstructionSet isa)41 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) {
42 // On ARM64 `neg` instructions are an alias of `sub` using the zero register
43 // as the first register input.
44 bool res = instr->IsAdd() || instr->IsAnd() ||
45 (isa == InstructionSet::kArm64 && instr->IsNeg()) ||
46 instr->IsOr() || instr->IsSub() || instr->IsXor();
47 return res;
48 }
49
50 // Check the specified sub is the last operation of the sequence:
51 // t1 = Shl
52 // t2 = Sub(t1, *)
53 // t3 = Sub(*, t2)
IsSubRightSubLeftShl(HSub * sub)54 inline bool IsSubRightSubLeftShl(HSub *sub) {
55 HInstruction* right = sub->GetRight();
56 return right->IsSub() && right->AsSub()->GetLeft()->IsShl();;
57 }
58
59 } // namespace helpers
60
61 bool TryCombineMultiplyAccumulate(HMul* mul, InstructionSet isa);
62 // For bitwise operations (And/Or/Xor) with a negated input, try to use
63 // a negated bitwise instruction.
64 bool TryMergeNegatedInput(HBinaryOperation* op);
65
66 bool TryExtractArrayAccessAddress(HInstruction* access,
67 HInstruction* array,
68 HInstruction* index,
69 size_t data_offset);
70
71 bool TryExtractVecArrayAccessAddress(HVecMemoryOperation* access, HInstruction* index);
72
73 // Try to replace
74 // Sub(c, Sub(a, b))
75 // with
76 // Add(c, Sub(b, a))
77 bool TryReplaceSubSubWithSubAdd(HSub* last_sub);
78
79 } // namespace art
80
81 #endif // ART_COMPILER_OPTIMIZING_INSTRUCTION_SIMPLIFIER_SHARED_H_
82