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Searched refs:GetId (Results 26 – 33 of 33) sorted by relevance

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/art/compiler/optimizing/
Dcode_generator_arm_vixl.h301 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_ARM()
339 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_ARM()
Dcode_generator_arm64.h301 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_ARM64()
423 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_ARM64()
Dscheduler.cc414 return DataType::TypeId(instruction->GetType()) + std::to_string(instruction->GetId()); in InstructionTypeId()
Dregister_allocator_linear_scan.cc966 << current->GetParent()->GetDefinedBy()->GetId() in AllocateBlockedReg()
Dnodes.h2301 int GetId() const { return id_; } in GetId() function
2406 DebugName() << " " << GetId(); in FOR_EACH_INSTRUCTION()
2435 result = (result * 31) + input->GetId(); in ComputeHashCode()
3626 if (left->GetId() > right->GetId()) { in OrderInputs()
Dinduction_var_analysis.cc1388 return std::to_string(fetch->GetId()) + ":" + fetch->DebugName(); in FetchToString()
Dloop_optimization.cc360 LOG(FATAL) << "Unsupported SIMD reduction " << reduction->GetId(); in GetReductionKind()
Dcode_generator_arm_vixl.cc6871 LOG(FATAL) << "Unreachable " << instruction->GetId(); in VisitIntermediateAddressIndex()
6876 LOG(FATAL) << "Unreachable " << instruction->GetId(); in VisitIntermediateAddressIndex()

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