| /art/test/dexdump/ |
| D | invoke-polymorphic.txt | 67 0x0000 - 0x0004 reg=0 this LMain;
101 0x0007 - 0x001e reg=0 handle Ljava/lang/invoke/MethodHandle;
102 0x0008 - 0x001e reg=5 o Ljava/lang/Object;
103 0x0011 - 0x001e reg=7 s Ljava/lang/String;
104 0x0016 - 0x001e reg=8 x I
105 0x0000 - 0x001e reg=9 args [Ljava/lang/String;
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| D | invoke-custom.txt | 69 0x0000 - 0x0004 reg=0 this LTestBadBootstrapArguments$TestersConstantCallSite;
70 0x0000 - 0x0004 reg=1 mh Ljava/lang/invoke/MethodHandle;
112 0x0000 - 0x0004 reg=0 this LTestBase;
145 0x0000 - 0x0022 reg=3 b1 B
146 0x0000 - 0x0022 reg=4 b2 B
179 0x0000 - 0x0022 reg=3 c1 C
180 0x0000 - 0x0022 reg=4 c2 C
214 0x0000 - 0x0024 reg=3 d1 D
215 0x0000 - 0x0024 reg=5 d2 D
249 0x0000 - 0x0024 reg=3 f1 F
[all …]
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| /art/test/510-checker-try-catch/smali/ |
| D | RegisterAllocator.smali | 23 ## CHECK-DAG: Phi reg:0 is_catch_phi:true locations:{{\[.*\]}}-><<SlotA1:\d+>>(sp)
24 ## CHECK-DAG: Phi reg:0 is_catch_phi:true locations:{{\[.*\]}}-><<SlotA2:\d+>>(sp)
25 ## CHECK-DAG: Phi reg:1 is_catch_phi:true locations:{{\[.*\]}}-><<SlotB:\d+>>(sp)
61 ## CHECK-DAG: Phi reg:0 is_catch_phi:true locations:{{\[.*\]}}->2x<<SlotB1:\d+>>(sp)
62 ## CHECK-DAG: Phi reg:0 is_catch_phi:true locations:{{\[.*\]}}->2x<<SlotB2:\d+>>(sp)
63 ## CHECK-DAG: Phi reg:2 is_catch_phi:true locations:{{\[.*\]}}-><<SlotA:\d+>>(sp)
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| /art/compiler/optimizing/ |
| D | stack_map_stream.cc | 249 DexRegisterLocation reg = current_dex_registers_[i]; in CreateDexRegisterMap() local
252 if (previous_dex_registers_[i] != reg || distance > kMaxDexRegisterMapSearchDistance) { in CreateDexRegisterMap()
254 entry[DexRegisterInfo::kKind] = static_cast<uint32_t>(reg.GetKind()); in CreateDexRegisterMap()
256 DexRegisterInfo::PackValue(reg.GetKind(), reg.GetValue()); in CreateDexRegisterMap()
257 uint32_t index = reg.IsLive() ? dex_register_catalog_.Dedup(&entry) : kNoValue; in CreateDexRegisterMap()
260 previous_dex_registers_[i] = reg; in CreateDexRegisterMap()
285 for (DexRegisterLocation reg : code_info.GetDexRegisterMapOf(stack_map)) { in CreateDexRegisterMap() local
286 CHECK_EQ((*expected_dex_registers)[expected_reg++], reg); in CreateDexRegisterMap()
290 for (DexRegisterLocation reg : map) { in CreateDexRegisterMap() local
291 CHECK_EQ((*expected_dex_registers)[expected_reg++], reg); in CreateDexRegisterMap()
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| D | locations.cc | 86 Location Location::ByteRegisterOrConstant(int reg, HInstruction* instruction) { in ByteRegisterOrConstant() argument
89 : Location::RegisterLocation(reg); in ByteRegisterOrConstant()
101 os << location.reg(); in operator <<()
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| D | code_generator_x86.h | 158 void SpillScratch(int reg) override;
159 void RestoreScratch(int reg) override;
164 void Exchange(Register reg, int mem);
165 void Exchange32(XmmRegister reg, int mem);
166 void Exchange128(XmmRegister reg, int mem);
419 void DumpCoreRegister(std::ostream& stream, int reg) const override;
420 void DumpFloatingPointRegister(std::ostream& stream, int reg) const override;
471 void LoadBootImageAddress(Register reg,
531 Address LiteralDoubleAddress(double v, HX86ComputeBaseMethodAddress* method_base, Register reg);
532 Address LiteralFloatAddress(float v, HX86ComputeBaseMethodAddress* method_base, Register reg);
[all …]
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| D | common_arm64.h | 68 return vixl::aarch64::Register::GetXRegFromCode(VIXLRegCodeFromART(location.reg())); in XRegisterFrom()
73 return vixl::aarch64::Register::GetWRegFromCode(VIXLRegCodeFromART(location.reg())); in WRegisterFrom()
92 return vixl::aarch64::VRegister::GetDRegFromCode(location.reg()); in DRegisterFrom()
97 return vixl::aarch64::VRegister::GetQRegFromCode(location.reg()); in QRegisterFrom()
102 return vixl::aarch64::VRegister::GetVRegFromCode(location.reg()); in VRegisterFrom()
107 return vixl::aarch64::VRegister::GetSRegFromCode(location.reg()); in SRegisterFrom()
112 return vixl::aarch64::VRegister::GetHRegFromCode(location.reg()); in HRegisterFrom()
205 inline Location LocationFrom(const vixl::aarch64::Register& reg) { in LocationFrom() argument
206 return Location::RegisterLocation(ARTRegCodeFromVIXL(reg.GetCode())); in LocationFrom()
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| D | ssa_liveness_analysis.cc | 336 return location.IsPair() ? location.low() : location.reg(); in RegisterOrLowRegister()
392 int reg = RegisterOrLowRegister(phi_location); in FindFirstRegisterHint() local
393 if (free_until[reg] >= use_position) { in FindFirstRegisterHint()
394 return reg; in FindFirstRegisterHint()
408 int reg = RegisterOrLowRegister(location); in FindFirstRegisterHint() local
409 if (free_until[reg] >= use_position) { in FindFirstRegisterHint()
410 return reg; in FindFirstRegisterHint()
424 int reg = RegisterOrLowRegister(expected); in FindFirstRegisterHint() local
425 if (free_until[reg] >= position) { in FindFirstRegisterHint()
426 return reg; in FindFirstRegisterHint()
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| D | code_generator.h | 102 bool IsCoreRegisterSaved(int reg) const { in IsCoreRegisterSaved() argument
103 return saved_core_stack_offsets_[reg] != kRegisterNotSaved; in IsCoreRegisterSaved()
106 bool IsFpuRegisterSaved(int reg) const { in IsFpuRegisterSaved() argument
107 return saved_fpu_stack_offsets_[reg] != kRegisterNotSaved; in IsFpuRegisterSaved()
110 uint32_t GetStackOffsetOfCoreRegister(int reg) const { in GetStackOffsetOfCoreRegister() argument
111 return saved_core_stack_offsets_[reg]; in GetStackOffsetOfCoreRegister()
114 uint32_t GetStackOffsetOfFpuRegister(int reg) const { in GetStackOffsetOfFpuRegister() argument
115 return saved_fpu_stack_offsets_[reg]; in GetStackOffsetOfFpuRegister()
274 virtual void DumpCoreRegister(std::ostream& stream, int reg) const = 0;
275 virtual void DumpFloatingPointRegister(std::ostream& stream, int reg) const = 0;
[all …]
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| D | common_arm.h | 67 return vixl::aarch32::Register(location.reg()); in RegisterFrom()
84 return vixl::aarch32::SRegister(location.reg()); in SRegisterFrom()
203 inline Location LocationFrom(const vixl::aarch32::Register& reg) { in LocationFrom() argument
204 return Location::RegisterLocation(reg.GetCode()); in LocationFrom()
207 inline Location LocationFrom(const vixl::aarch32::SRegister& reg) { in LocationFrom() argument
208 return Location::FpuRegisterLocation(reg.GetCode()); in LocationFrom()
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| /art/runtime/ |
| D | stack.cc | 182 uint16_t reg = accessor.RegistersSize() - accessor.InsSize(); in GetThisObject() local
184 if (!GetVReg(m, reg, kReferenceVReg, &value)) { in GetThisObject()
308 uint32_t reg = dex_register_map[vreg].GetMachineRegister(); in GetVRegFromOptimizedCode() local
309 if (kind == kReferenceVReg && !(register_mask & (1 << reg))) { in GetVRegFromOptimizedCode()
312 return GetRegisterIfAccessible(reg, kind, val); in GetVRegFromOptimizedCode()
320 uint32_t reg = dex_register_map[vreg].GetMachineRegister(); in GetVRegFromOptimizedCode() local
321 return GetRegisterIfAccessible(reg, kind, val); in GetVRegFromOptimizedCode()
365 bool StackVisitor::GetRegisterIfAccessible(uint32_t reg, VRegKind kind, uint32_t* val) const { in GetRegisterIfAccessible() argument
371 reg = (kind == kDoubleHiVReg) ? (2 * reg + 1) : (2 * reg); in GetRegisterIfAccessible()
374 if (!IsAccessibleRegister(reg, is_float)) { in GetRegisterIfAccessible()
[all …]
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| D | quick_exception_handler.cc | 439 for (size_t reg = 0; reg < num_regs; ++reg) { in HandleNterpDeoptimization() local
440 if (updated_vregs != nullptr && updated_vregs[reg]) { in HandleNterpDeoptimization()
444 StackReference<mirror::Object>* ref_addr = vreg_ref_base + reg; in HandleNterpDeoptimization()
447 new_frame->SetVRegReference(reg, ref); in HandleNterpDeoptimization()
449 new_frame->SetVReg(reg, vreg_int_base[reg]); in HandleNterpDeoptimization()
506 uint32_t reg = vreg_map[vreg].GetMachineRegister(); in HandleOptimizingDeoptimization() local
507 bool result = GetRegisterIfAccessible(reg, ToVRegKind(location), &value); in HandleOptimizingDeoptimization()
510 if (((1u << reg) & register_mask) != 0) { in HandleOptimizingDeoptimization()
540 static VRegKind GetVRegKind(uint16_t reg, const std::vector<int32_t>& kinds) { in GetVRegKind() argument
541 return static_cast<VRegKind>(kinds[reg * 2]); in GetVRegKind()
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| D | stack_map.cc | 199 for (uint32_t reg = 0; reg < end; reg += kNumBits) { in DecodeDexRegisterMap() local
201 uint32_t bits = mask.LoadBits(reg, std::min<uint32_t>(end - reg, kNumBits)); in DecodeDexRegisterMap()
204 if (regs[reg + bit].GetKind() == DexRegisterLocation::Kind::kInvalid) { in DecodeDexRegisterMap()
205 regs[reg + bit] = GetDexRegisterCatalogEntry(dex_register_maps_.Get(map_index)); in DecodeDexRegisterMap()
252 DexRegisterLocation reg = (*this)[i]; in Dump() local
253 if (reg.IsLive()) { in Dump()
254 vios->Stream() << "v" << i << ":" << reg << " "; in Dump()
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| D | common_dex_operations.h | 212 ObjPtr<mirror::Object> reg = value.GetL(); in DoFieldPutCommon() local
213 if (do_assignability_check && reg != nullptr) { in DoFieldPutCommon()
220 HandleWrapperObjPtr<mirror::Object> h_reg(hs.NewHandleWrapper(®)); in DoFieldPutCommon()
230 if (UNLIKELY(!reg->VerifierInstanceOf(field_class))) { in DoFieldPutCommon()
235 reg->GetClass()->GetDescriptor(&temp1), in DoFieldPutCommon()
241 field->SetObj<transaction_active>(obj, reg); in DoFieldPutCommon()
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| D | check_reference_map_visitor.h | 87 int reg = registers[i]; in CheckOptimizedMethod() local
88 CHECK_LT(reg, accessor.RegistersSize()); in CheckOptimizedMethod()
89 DexRegisterLocation location = dex_register_map[reg]; in CheckOptimizedMethod()
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 332 auto get_mask = [](ManagedRegister reg) -> uint64_t { in MoveArguments() argument
333 Arm64ManagedRegister arm64_reg = reg.AsArm64(); in MoveArguments()
597 Arm64ManagedRegister reg = mreg.AsArm64(); in SignExtend() local
599 CHECK(reg.IsWRegister()) << reg; in SignExtend()
601 ___ Sxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in SignExtend()
603 ___ Sxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in SignExtend()
608 Arm64ManagedRegister reg = mreg.AsArm64(); in ZeroExtend() local
610 CHECK(reg.IsWRegister()) << reg; in ZeroExtend()
612 ___ Uxtb(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in ZeroExtend()
614 ___ Uxth(reg_w(reg.AsWRegister()), reg_w(reg.AsWRegister())); in ZeroExtend()
[all …]
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| D | managed_register_arm64.cc | 102 std::ostream& operator<<(std::ostream& os, const Arm64ManagedRegister& reg) { in operator <<() argument
103 reg.Print(os); in operator <<()
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| /art/compiler/utils/x86_64/ |
| D | constants_x86_64.h | 47 std::ostream& operator<<(std::ostream& os, const CpuRegister& reg);
68 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg);
82 std::ostream& operator<<(std::ostream& os, const X87Register& reg);
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| D | jni_macro_assembler_x86_64.cc | 27 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() argument
28 return dwarf::Reg::X86_64Core(static_cast<int>(reg)); in DWARFReg()
30 static dwarf::Reg DWARFReg(FloatRegister reg) { in DWARFReg() argument
31 return dwarf::Reg::X86_64Fp(static_cast<int>(reg)); in DWARFReg()
320 X86_64ManagedRegister reg = mreg.AsX86_64(); in SignExtend() local
322 CHECK(reg.IsCpuRegister()) << reg; in SignExtend()
324 __ movsxb(reg.AsCpuRegister(), reg.AsCpuRegister()); in SignExtend()
326 __ movsxw(reg.AsCpuRegister(), reg.AsCpuRegister()); in SignExtend()
331 X86_64ManagedRegister reg = mreg.AsX86_64(); in ZeroExtend() local
333 CHECK(reg.IsCpuRegister()) << reg; in ZeroExtend()
[all …]
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| /art/runtime/interpreter/mterp/arm64ng/ |
| D | main.S | 148 .macro FETCH_ADVANCE_INST_RB reg argument
149 add xPC, xPC, \reg, sxtw
159 .macro FETCH reg, count
160 ldrh \reg, [xPC, #((\count)*2)]
163 .macro FETCH_S reg, count
164 ldrsh \reg, [xPC, #((\count)*2)]
172 .macro FETCH_B reg, count, byte
173 ldrb \reg, [xPC, #((\count)*2+(\byte))]
179 .macro GET_INST_OPCODE reg argument
180 and \reg, xINST, #255
[all …]
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| /art/runtime/arch/arm/ |
| D | quick_entrypoints_arm.S | 2080 .macro CONDITIONAL_CBZ reg, reg_if, dest
2081 .ifc \reg, \reg_if
2082 cbz \reg, \dest
2086 .macro CONDITIONAL_CMPBZ reg, reg_if, dest
2087 .ifc \reg, \reg_if
2088 cmp \reg, #0
2094 .macro SMART_CBZ reg, dest
2095 CONDITIONAL_CBZ \reg, r0, \dest
2096 CONDITIONAL_CBZ \reg, r1, \dest
2097 CONDITIONAL_CBZ \reg, r2, \dest
[all …]
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 42 static dwarf::Reg DWARFReg(Register reg) { in DWARFReg() argument
43 return dwarf::Reg::X86Core(static_cast<int>(reg)); in DWARFReg()
282 X86ManagedRegister reg = mreg.AsX86(); in SignExtend() local
284 CHECK(reg.IsCpuRegister()) << reg; in SignExtend()
286 __ movsxb(reg.AsCpuRegister(), reg.AsByteRegister()); in SignExtend()
288 __ movsxw(reg.AsCpuRegister(), reg.AsCpuRegister()); in SignExtend()
293 X86ManagedRegister reg = mreg.AsX86(); in ZeroExtend() local
295 CHECK(reg.IsCpuRegister()) << reg; in ZeroExtend()
297 __ movzxb(reg.AsCpuRegister(), reg.AsByteRegister()); in ZeroExtend()
299 __ movzxw(reg.AsCpuRegister(), reg.AsCpuRegister()); in ZeroExtend()
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| /art/runtime/interpreter/mterp/x86/ |
| D | array.S | 73 %def op_aput(reg="rINST", store="movl", shift="4", data_offset="MIRROR_INT_ARRAY_DATA_OFFSET"):
91 $store $reg, (%eax)
95 % op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BOOLEAN_ARRAY_DATA_OFFSET")
98 % op_aput(reg="rINSTbl", store="movb", shift="1", data_offset="MIRROR_BYTE_ARRAY_DATA_OFFSET")
101 % op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_CHAR_ARRAY_DATA_OFFSET")
121 % op_aput(reg="rINSTw", store="movw", shift="2", data_offset="MIRROR_SHORT_ARRAY_DATA_OFFSET")
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| /art/test/128-reg-spill-on-implicit-nullcheck/ |
| D | info.txt | 1 This is a compiler reggression test for missing reg spilling on implicit nullcheck.
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| /art/compiler/utils/arm/ |
| D | managed_register_arm.cc | 92 std::ostream& operator<<(std::ostream& os, const ArmManagedRegister& reg) { in operator <<() argument
93 reg.Print(os); in operator <<()
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