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Searched refs:instr (Results 1 – 25 of 56) sorted by relevance

123

/art/runtime/interpreter/mterp/arm64/
Darithmetic.S1 %def binop(preinstr="", result="w0", chkzero="0", instr=""):
29 $instr // $result<- op, w0-w3 changed
35 %def binop2addr(preinstr="", result="w0", chkzero="0", instr=""):
60 $instr // $result<- op, w0-w3 changed
66 %def binopLit16(preinstr="", result="w0", chkzero="0", instr=""):
89 $instr // $result<- op, w0-w3 changed
95 %def binopLit8(extract="asr w1, w3, #8", preinstr="", result="w0", chkzero="0", instr=""):
124 $instr // $result<- op, w0-w3 changed
130 %def binopWide(preinstr="", instr="add x0, x1, x2", result="x0", r1="x1", r2="x2", chkzero="0"):
155 $instr // $result<- op, w0-w4 changed
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Dfloating_point.S1 %def fbinop(instr=""):
14 $instr // s0<- op
21 %def fbinopWide(instr="fadd d0, d1, d2", result="d0", r1="d1", r2="d2"):
33 $instr // $result<- op, w0-w4 changed
38 %def fbinop2addr(instr=""):
51 $instr // s2<- op
57 %def fbinopWide2addr(instr="fadd d0, d0, d1", r0="d0", r1="d1"):
67 $instr // result<- op
97 %def funopNarrow(srcreg="s0", tgtreg="d0", instr=""):
110 $instr // d0<- op
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/art/compiler/optimizing/
Dscheduler_arm64.cc26 void SchedulingLatencyVisitorARM64::VisitBinaryOperation(HBinaryOperation* instr) { in VisitBinaryOperation() argument
27 last_visited_latency_ = DataType::IsFloatingPointType(instr->GetResultType()) in VisitBinaryOperation()
50 HIntermediateAddressIndex* instr ATTRIBUTE_UNUSED) { in VisitIntermediateAddressIndex()
82 void SchedulingLatencyVisitorARM64::VisitDiv(HDiv* instr) { in VisitDiv() argument
83 DataType::Type type = instr->GetResultType(); in VisitDiv()
93 if (instr->GetRight()->IsConstant()) { in VisitDiv()
94 int64_t imm = Int64FromConstant(instr->GetRight()->AsConstant()); in VisitDiv()
135 void SchedulingLatencyVisitorARM64::VisitMul(HMul* instr) { in VisitMul() argument
136 last_visited_latency_ = DataType::IsFloatingPointType(instr->GetResultType()) in VisitMul()
196 void SchedulingLatencyVisitorARM64::VisitTypeConversion(HTypeConversion* instr) { in VisitTypeConversion() argument
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Dcommon_arm.h87 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr) { in OutputSRegister() argument
88 DataType::Type type = instr->GetType(); in OutputSRegister()
90 return SRegisterFrom(instr->GetLocations()->Out()); in OutputSRegister()
93 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) { in OutputDRegister() argument
94 DataType::Type type = instr->GetType(); in OutputDRegister()
96 return DRegisterFrom(instr->GetLocations()->Out()); in OutputDRegister()
99 inline vixl::aarch32::VRegister OutputVRegister(HInstruction* instr) { in OutputVRegister() argument
100 DataType::Type type = instr->GetType(); in OutputVRegister()
102 return OutputSRegister(instr); in OutputVRegister()
104 return OutputDRegister(instr); in OutputVRegister()
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Dreference_type_propagation.cc63 void VisitLoadMethodHandle(HLoadMethodHandle* instr) override;
64 void VisitLoadMethodType(HLoadMethodType* instr) override;
65 void VisitLoadString(HLoadString* instr) override;
66 void VisitLoadException(HLoadException* instr) override;
67 void VisitNewArray(HNewArray* instr) override;
68 void VisitParameterValue(HParameterValue* instr) override;
69 void VisitInstanceFieldGet(HInstanceFieldGet* instr) override;
70 void VisitStaticFieldGet(HStaticFieldGet* instr) override;
71 void VisitUnresolvedInstanceFieldGet(HUnresolvedInstanceFieldGet* instr) override;
72 void VisitUnresolvedStaticFieldGet(HUnresolvedStaticFieldGet* instr) override;
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Dcommon_arm64.h81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister() argument
82 return RegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt() argument
86 return RegisterFrom(instr->GetLocations()->InAt(input_index), in InputRegisterAt()
87 instr->InputAt(input_index)->GetType()); in InputRegisterAt()
120 inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister() argument
121 return FPRegisterFrom(instr->GetLocations()->Out(), instr->GetType()); in OutputFPRegister()
124 inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt() argument
125 return FPRegisterFrom(instr->GetLocations()->InAt(input_index), in InputFPRegisterAt()
126 instr->InputAt(input_index)->GetType()); in InputFPRegisterAt()
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Dinstruction_simplifier_shared.h41 inline bool HasShifterOperand(HInstruction* instr, InstructionSet isa) { in HasShifterOperand() argument
44 bool res = instr->IsAdd() || instr->IsAnd() || in HasShifterOperand()
45 (isa == InstructionSet::kArm64 && instr->IsNeg()) || in HasShifterOperand()
46 instr->IsOr() || instr->IsSub() || instr->IsXor(); in HasShifterOperand()
Dselect_generator_test.cc37 void ConstructBasicGraphForSelect(HInstruction* instr) { in ConstructBasicGraphForSelect() argument
58 then_block->AddInstruction(instr); in ConstructBasicGraphForSelect()
65 phi->AddInput(instr); in ConstructBasicGraphForSelect()
82 HDivZeroCheck* instr = new (GetAllocator()) HDivZeroCheck(parameters_[0], 0); in TEST_F() local
83 ConstructBasicGraphForSelect(instr); in TEST_F()
87 ManuallyBuildEnvFor(instr, &current_locals); in TEST_F()
95 HAdd* instr = new (GetAllocator()) HAdd(DataType::Type::kInt32, in TEST_F() local
98 ConstructBasicGraphForSelect(instr); in TEST_F()
Dscheduler_arm.cc32 void SchedulingLatencyVisitorARM::HandleBinaryOperationLantencies(HBinaryOperation* instr) { in HandleBinaryOperationLantencies() argument
33 switch (instr->GetResultType()) { in HandleBinaryOperationLantencies()
51 void SchedulingLatencyVisitorARM::VisitAdd(HAdd* instr) { in VisitAdd() argument
52 HandleBinaryOperationLantencies(instr); in VisitAdd()
55 void SchedulingLatencyVisitorARM::VisitSub(HSub* instr) { in VisitSub() argument
56 HandleBinaryOperationLantencies(instr); in VisitSub()
59 void SchedulingLatencyVisitorARM::VisitMul(HMul* instr) { in VisitMul() argument
60 switch (instr->GetResultType()) { in VisitMul()
75 void SchedulingLatencyVisitorARM::HandleBitwiseOperationLantencies(HBinaryOperation* instr) { in HandleBitwiseOperationLantencies() argument
76 switch (instr->GetResultType()) { in HandleBitwiseOperationLantencies()
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Dscheduler_arm64.h131 void HandleSimpleArithmeticSIMD(HVecOperation *instr);
163 bool IsSchedulingBarrier(const HInstruction* instr) const override { in IsSchedulingBarrier() argument
164 return HScheduler::IsSchedulingBarrier(instr) || in IsSchedulingBarrier()
165 instr->IsVecReduce() || in IsSchedulingBarrier()
166 instr->IsVecExtractScalar() || in IsSchedulingBarrier()
167 instr->IsVecSetScalars() || in IsSchedulingBarrier()
168 instr->IsVecReplicateScalar(); in IsSchedulingBarrier()
Dselect_generator.cc122 HInstruction* instr = true_block->GetFirstInstruction(); in Run() local
123 DCHECK(!instr->CanThrow()); in Run()
124 instr->MoveBefore(if_instruction); in Run()
127 HInstruction* instr = false_block->GetFirstInstruction(); in Run() local
128 DCHECK(!instr->CanThrow()); in Run()
129 instr->MoveBefore(if_instruction); in Run()
Dscheduler.h159 SchedulingNode(HInstruction* instr, ScopedArenaAllocator* allocator, bool is_scheduling_barrier) in SchedulingNode() argument
163 instruction_(instr), in SchedulingNode()
330 SchedulingNode* AddNode(HInstruction* instr, bool is_scheduling_barrier = false) {
332 new (allocator_) SchedulingNode(instr, allocator_, is_scheduling_barrier));
334 nodes_map_.insert(std::make_pair(instr, std::move(node)));
340 SchedulingNode* GetNode(const HInstruction* instr) const { in GetNode() argument
341 auto it = nodes_map_.find(instr); in GetNode()
Dscheduler_arm.h122 void HandleCondition(HCondition* instr);
123 void HandleBinaryOperationLantencies(HBinaryOperation* instr);
124 void HandleBitwiseOperationLantencies(HBinaryOperation* instr);
125 void HandleShiftLatencies(HBinaryOperation* instr);
/art/disassembler/
Ddisassembler_arm64.cc44 void CustomDisassembler::AppendRegisterNameToOutput(const Instruction* instr, in AppendRegisterNameToOutput() argument
46 USE(instr); in AppendRegisterNameToOutput()
58 Disassembler::AppendRegisterNameToOutput(instr, reg); in AppendRegisterNameToOutput()
61 void CustomDisassembler::VisitLoadLiteral(const Instruction* instr) { in VisitLoadLiteral() argument
62 Disassembler::VisitLoadLiteral(instr); in VisitLoadLiteral()
71 void* data_address = instr->GetLiteralAddress<void*>(); in VisitLoadLiteral()
78 Instr op = instr->Mask(LoadLiteralMask); in VisitLoadLiteral()
100 void CustomDisassembler::VisitLoadStoreUnsignedOffset(const Instruction* instr) { in VisitLoadStoreUnsignedOffset() argument
101 Disassembler::VisitLoadStoreUnsignedOffset(instr); in VisitLoadStoreUnsignedOffset()
103 if (instr->GetRn() == TR) { in VisitLoadStoreUnsignedOffset()
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Ddisassembler_x86.cc174 RegFile dst_reg_file, const uint8_t** instr, in DumpAddress() argument
179 *address_bits = *reinterpret_cast<const uint32_t*>(*instr); in DumpAddress()
182 address << StringPrintf("[RIP + 0x%x]", *reinterpret_cast<const uint32_t*>(*instr)); in DumpAddress()
184 (*instr) += 4; in DumpAddress()
186 uint8_t sib = **instr; in DumpAddress()
187 (*instr)++; in DumpAddress()
219 address << StringPrintf(" + %d", *reinterpret_cast<const int32_t*>(*instr)); in DumpAddress()
222 *address_bits = *reinterpret_cast<const uint32_t*>(*instr); in DumpAddress()
225 (*instr) += 4; in DumpAddress()
228 address << StringPrintf(" + %d", *reinterpret_cast<const int8_t*>(*instr)); in DumpAddress()
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Ddisassembler_x86.h36 size_t DumpNops(std::ostream& os, const uint8_t* instr);
37 size_t DumpInstruction(std::ostream& os, const uint8_t* instr);
41 RegFile src_reg_file, RegFile dst_reg_file, const uint8_t** instr,
Ddisassembler_arm64.h47 void AppendRegisterNameToOutput(const vixl::aarch64::Instruction* instr,
51 void VisitLoadLiteral(const vixl::aarch64::Instruction* instr) override;
54 void VisitLoadStoreUnsignedOffset(const vixl::aarch64::Instruction* instr) override;
/art/runtime/interpreter/mterp/x86_64/
Darithmetic.S176 %def binop(result="%eax", instr=""):
190 $instr VREG_ADDRESS(%rcx),%eax
194 %def binop1(wide="0", instr=""):
205 $instr # ex: addl %ecx,%eax
209 $instr # ex: addl %ecx,%eax
214 %def binop2addr(result="%eax", instr=""):
230 $instr %eax, VREG_ADDRESS(%rcx)
234 %def binopLit16(result="%eax", instr=""):
250 $instr # for example: addl %ecx, %eax
254 %def binopLit8(result="%eax", instr=""):
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Dfloating_point.S55 %def sseBinop(instr="", suff=""):
60 v${instr}${suff} VREG_ADDRESS(%rax), %xmm0, %xmm0
65 ${instr}${suff} VREG_ADDRESS(%rax), %xmm0
72 %def sseBinop2Addr(instr="", suff=""):
78 v${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0, %xmm0
83 ${instr}${suff} VREG_ADDRESS(rINSTq), %xmm0
91 % sseBinop(instr="adds", suff="d")
94 % sseBinop2Addr(instr="adds", suff="d")
97 % sseBinop(instr="adds", suff="s")
100 % sseBinop2Addr(instr="adds", suff="s")
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/art/runtime/
Dinstrumentation_test.cc196 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in CheckConfigureStubs() local
202 instr->ConfigureStubs(key, level); in CheckConfigureStubs()
223 instrumentation::Instrumentation* instr = Runtime::Current()->GetInstrumentation(); in TestEvent() local
228 instr->AddListener(&listener, instrumentation_event); in TestEvent()
236 EXPECT_TRUE(HasEventListener(instr, instrumentation_event)); in TestEvent()
238 ReportEvent(instr, in TestEvent()
252 instr->RemoveListener(&listener, instrumentation_event); in TestEvent()
256 EXPECT_FALSE(HasEventListener(instr, instrumentation_event)); in TestEvent()
258 ReportEvent(instr, in TestEvent()
355 static bool HasEventListener(const instrumentation::Instrumentation* instr, uint32_t event_type) in HasEventListener() argument
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Dcommon_throws.cc463 static bool IsValidImplicitCheck(uintptr_t addr, const Instruction& instr) in IsValidImplicitCheck() argument
469 switch (instr.Opcode()) { in IsValidImplicitCheck()
577 const Instruction& instr = accessor.InstructionAt(throw_dex_pc); in ThrowNullPointerExceptionFromDexPC() local
578 if (check_address && !IsValidImplicitCheck(addr, instr)) { in ThrowNullPointerExceptionFromDexPC()
583 << instr.DumpString(dex_file) in ThrowNullPointerExceptionFromDexPC()
588 switch (instr.Opcode()) { in ThrowNullPointerExceptionFromDexPC()
590 ThrowNullPointerExceptionForMethodAccess(instr.VRegB_35c(), kDirect); in ThrowNullPointerExceptionFromDexPC()
593 ThrowNullPointerExceptionForMethodAccess(instr.VRegB_3rc(), kDirect); in ThrowNullPointerExceptionFromDexPC()
596 ThrowNullPointerExceptionForMethodAccess(instr.VRegB_35c(), kVirtual); in ThrowNullPointerExceptionFromDexPC()
599 ThrowNullPointerExceptionForMethodAccess(instr.VRegB_3rc(), kVirtual); in ThrowNullPointerExceptionFromDexPC()
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/art/runtime/interpreter/mterp/x86/
Dfloating_point.S37 %def fpcvt(instr="", load="", store="", wide="0"):
46 $instr
55 %def sseBinop(instr="", suff=""):
60 v${instr}${suff} VREG_ADDRESS(%eax), %xmm0, %xmm0
65 ${instr}${suff} VREG_ADDRESS(%eax), %xmm0
72 %def sseBinop2Addr(instr="", suff=""):
78 v${instr}${suff} VREG_ADDRESS(rINST), %xmm0, %xmm0
83 ${instr}${suff} VREG_ADDRESS(rINST), %xmm0
91 % sseBinop(instr="adds", suff="d")
94 % sseBinop2Addr(instr="adds", suff="d")
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Darithmetic.S142 %def binop(result="%eax", instr=""):
156 $instr VREG_ADDRESS(%ecx), %eax
160 %def binop1(result="%eax", tmp="%ecx", instr=""):
170 $instr # ex: addl %ecx,%eax
174 %def binop2addr(result="%eax", instr=""):
190 $instr %eax, VREG_ADDRESS(%ecx)
194 %def binopLit16(result="%eax", instr=""):
210 $instr # for example: addl %ecx, %eax
214 %def binopLit8(result="%eax", instr=""):
229 $instr # ex: addl %ecx,%eax
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/art/runtime/interpreter/mterp/arm/
Dfloating_point.S1 %def fbinop(instr=""):
20 $instr @ s2<- op
25 %def fbinop2addr(instr=""):
41 $instr @ s2<- op
458 % binopWide(instr="bl fmod")
462 % binopWide2addr(instr="bl fmod")
466 % binop(instr="bl fmodf")
470 % binop2addr(instr="bl fmodf")
473 % fbinopWide(instr="fsubd d2, d0, d1")
476 % fbinopWide2addr(instr="fsubd d2, d0, d1")
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Darithmetic.S1 %def binop(preinstr="", result="r0", chkzero="0", instr=""):
31 $instr @ $result<- op, r0-r3 changed
37 %def binop2addr(preinstr="", result="r0", chkzero="0", instr=""):
64 $instr @ $result<- op, r0-r3 changed
70 %def binopLit16(result="r0", chkzero="0", instr=""):
94 $instr @ $result<- op, r0-r3 changed
100 %def binopLit8(extract="asr r1, r3, #8", result="r0", chkzero="0", instr=""):
130 $instr @ $result<- op, r0-r3 changed
136 %def binopWide(preinstr="", result0="r0", result1="r1", chkzero="0", instr=""):
169 $instr @ result<- op, r0-r3 changed
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