| /art/runtime/arch/arm64/ |
| D | asm_support_arm64.S | 137 .macro SAVE_TWO_REGS_BASE base, reg1, reg2, offset
138 stp \reg1, \reg2, [\base, #(\offset)]
139 .cfi_rel_offset \reg1, (\offset)
143 .macro SAVE_TWO_REGS reg1, reg2, offset
144 SAVE_TWO_REGS_BASE sp, \reg1, \reg2, \offset
147 .macro RESTORE_TWO_REGS_BASE base, reg1, reg2, offset
148 ldp \reg1, \reg2, [\base, #(\offset)]
149 .cfi_restore \reg1
153 .macro RESTORE_TWO_REGS reg1, reg2, offset
154 RESTORE_TWO_REGS_BASE sp, \reg1, \reg2, \offset
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| D | quick_entrypoints_arm64.S | 34 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
35 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
37 .cfi_rel_offset \reg1, 0
41 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment
42 ldp \reg1, \reg2, [sp], #(\frame_adjustment)
43 .cfi_restore \reg1
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| /art/runtime/interpreter/mterp/arm64/ |
| D | main.S | 316 .macro SAVE_TWO_REGS reg1, reg2, offset
317 stp \reg1, \reg2, [sp, #(\offset)]
318 .cfi_rel_offset \reg1, (\offset)
325 .macro RESTORE_TWO_REGS reg1, reg2, offset
326 ldp \reg1, \reg2, [sp, #(\offset)]
327 .cfi_restore \reg1
334 .macro SAVE_TWO_REGS_INCREASE_FRAME reg1, reg2, frame_adjustment
335 stp \reg1, \reg2, [sp, #-(\frame_adjustment)]!
337 .cfi_rel_offset \reg1, 0
344 .macro RESTORE_TWO_REGS_DECREASE_FRAME reg1, reg2, frame_adjustment
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| /art/compiler/utils/ |
| D | assembler_test.h | 194 for (auto reg1 : reg1_registers) { variable
199 (assembler_.get()->*f)(*reg1, *reg2, new_imm * multiplier + bias);
203 std::string reg1_string = (this->*GetName1)(*reg1);
249 for (auto reg1 : reg1_registers) { in RepeatTemplatedRegistersImmBits() local
255 (assembler_.get()->*f)(*reg1, *reg2, *reg3, new_imm + bias); in RepeatTemplatedRegistersImmBits()
259 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedRegistersImmBits()
311 for (auto reg1 : reg1_registers) { in RepeatTemplatedImmBitsRegisters() local
316 (assembler_.get()->*f)(new_imm, *reg1, *reg2); in RepeatTemplatedImmBitsRegisters()
320 std::string reg1_string = (this->*GetName1)(*reg1); in RepeatTemplatedImmBitsRegisters()
1273 for (auto reg1 : reg1_registers) { in RepeatTemplatedRegisters() local
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| /art/runtime/interpreter/mterp/arm/ |
| D | main.S | 301 .macro GET_VREG_WIDE_BY_ADDR reg0, reg1, addr
302 ldmia \addr, {\reg0, \reg1}
304 .macro SET_VREG_WIDE_BY_ADDR reg0, reg1, addr
305 stmia \addr, {\reg0, \reg1}
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 720 void cmpl(CpuRegister reg0, CpuRegister reg1);
725 void cmpq(CpuRegister reg0, CpuRegister reg1);
730 void testl(CpuRegister reg1, CpuRegister reg2);
734 void testq(CpuRegister reg1, CpuRegister reg2);
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| D | assembler_x86_64.cc | 3895 void X86_64Assembler::cmpl(CpuRegister reg0, CpuRegister reg1) { in cmpl() argument
3897 EmitOptionalRex32(reg0, reg1); in cmpl()
3899 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpl()
3927 void X86_64Assembler::cmpq(CpuRegister reg0, CpuRegister reg1) { in cmpq() argument
3929 EmitRex64(reg0, reg1); in cmpq()
3931 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpq()
3975 void X86_64Assembler::testl(CpuRegister reg1, CpuRegister reg2) { in testl() argument
3977 EmitOptionalRex32(reg1, reg2); in testl()
3979 EmitRegisterOperand(reg1.LowBits(), reg2.LowBits()); in testl()
4017 void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) { in testq() argument
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| /art/compiler/utils/x86/ |
| D | assembler_x86.h | 681 void cmpl(Register reg0, Register reg1);
687 void testl(Register reg1, Register reg2);
689 void testl(Register reg1, const Address& address);
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| D | assembler_x86.cc | 2925 void X86Assembler::cmpl(Register reg0, Register reg1) { in cmpl() argument
2928 EmitOperand(reg0, Operand(reg1)); in cmpl()
2966 void X86Assembler::testl(Register reg1, Register reg2) { in testl() argument
2969 EmitRegisterOperand(reg1, reg2); in testl()
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| /art/compiler/optimizing/ |
| D | code_generator_x86_64.h | 167 void Exchange64(CpuRegister reg1, CpuRegister reg2);
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| D | code_generator_arm_vixl.cc | 4612 vixl32::Register reg1 = InputRegisterAt(rem, 0); in VisitRem() local
4622 __ Sdiv(temp, reg1, reg2); in VisitRem()
4623 __ Mls(out_reg, temp, reg2, reg1); in VisitRem()
4626 DCHECK(reg1.Is(calling_convention.GetRegisterAt(0))); in VisitRem()
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| D | code_generator_x86_64.cc | 5926 void ParallelMoveResolverX86_64::Exchange64(CpuRegister reg1, CpuRegister reg2) { in Exchange64() argument
5927 __ movq(CpuRegister(TMP), reg1); in Exchange64()
5928 __ movq(reg1, reg2); in Exchange64()
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