1 /* 2 * Copyright (c) 2015-2019, The Linux Foundation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without modification, are permitted 5 * provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright notice, this list of 7 * conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright notice, this list of 9 * conditions and the following disclaimer in the documentation and/or other materials provided 10 * with the distribution. 11 * * Neither the name of The Linux Foundation nor the names of its contributors may be used to 12 * endorse or promote products derived from this software without specific prior written 13 * permission. 14 * 15 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 16 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 17 * NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 21 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 22 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 23 */ 24 25 #ifndef __HW_INFO_TYPES_H__ 26 #define __HW_INFO_TYPES_H__ 27 28 #include <stdint.h> 29 #include <core/display_interface.h> 30 #include <core/core_interface.h> 31 #include <utils/locker.h> 32 #include <utils/debug.h> 33 #include <vector> 34 #include <map> 35 #include <string> 36 #include <bitset> 37 #include <memory> 38 39 namespace sdm { 40 using std::string; 41 42 const int kMaxSDELayers = 16; // Maximum number of layers that can be handled by MDP5 hardware 43 // in a given layer stack. 44 #define MAX_PLANES 4 45 #define MAX_DETAIL_ENHANCE_CURVE 3 46 #define MAJOR 28 47 #define MINOR 16 48 #define SDEVERSION(major, minor, hw_rev) ((major) << MAJOR) | ((minor) << MINOR) | (hw_rev) 49 50 // CSC Max Size 51 #define MAX_CSC_MATRIX_COEFF_SIZE 9 52 #define MAX_CSC_CLAMP_SIZE 6 53 #define MAX_CSC_BIAS_SIZE 3 54 55 enum HWDeviceType { 56 kDeviceBuiltIn, 57 kDevicePluggable, 58 kDeviceVirtual, 59 kDeviceRotator, 60 kDeviceMax, 61 }; 62 63 enum HWBlockType { 64 kHWBuiltIn, 65 kHWPluggable, 66 kHWWriteback0, 67 kHWWriteback1, 68 kHWWriteback2, 69 kHWBlockMax 70 }; 71 72 enum HWDisplayMode { 73 kModeDefault, 74 kModeVideo, 75 kModeCommand, 76 }; 77 78 enum PipeType { 79 kPipeTypeUnused, 80 kPipeTypeVIG, 81 kPipeTypeRGB, 82 kPipeTypeDMA, 83 kPipeTypeCursor, 84 }; 85 86 enum HWSubBlockType { 87 kHWVIGPipe, 88 kHWRGBPipe, 89 kHWDMAPipe, 90 kHWCursorPipe, 91 kHWRotatorInput, 92 kHWRotatorOutput, 93 kHWWBIntfOutput, 94 kHWDestinationScalar, 95 kHWSubBlockMax, 96 }; 97 98 enum HWAlphaInterpolation { 99 kInterpolationPixelRepeat, 100 kInterpolationBilinear, 101 kInterpolation2D, 102 kInterpolationMax, 103 }; 104 105 enum HWBlendingFilter { 106 kBlendFilterCircular, 107 kBlendFilterSeparable, 108 kBlendFilterMax, 109 }; 110 111 enum HWPipeFlags { 112 kIGC = 1 << 0, 113 kMultiRect = 1 << 1, 114 kMultiRectParallelMode = 1 << 2, 115 kFlipVertical = 1 << 5, 116 kFlipHorizontal = 1 << 6, 117 kSecure = 1 << 7, 118 kDisplaySecure = 1 << 8, 119 kCameraSecure = 1 << 9, 120 kInterlaced = 1 << 10, 121 kUpdating = 1 < 11, 122 kSolidFill = 1 << 12, 123 kTonemap1d = 1 << 13, 124 kTonemap3d = 1 << 14, 125 }; 126 127 enum HWAVRModes { 128 kContinuousMode, // Mode to enable AVR feature for every frame. 129 kOneShotMode, // Mode to enable AVR feature for particular frame. 130 }; 131 132 enum HWTopology { 133 kUnknown, 134 kSingleLM, 135 kSingleLMDSC, 136 kDualLM, 137 kDualLMDSC, 138 kDualLMMerge, 139 kDualLMMergeDSC, 140 kDualLMDSCMerge, 141 kPPSplit, 142 }; 143 144 enum HwHdrEotf { 145 kHdrEOTFInvalid = 0, 146 kHdrEOTFSDR = 0x1, 147 kHdrEOTFHdrLumRange = 0x2, 148 kHdrEOTFHDR10 = 0x4, 149 kHdrEOTFHLG = 0x8, 150 }; 151 152 enum HWSrcTonemap { 153 kSrcTonemapNone, 154 kSrcTonemap1d, // DMA 155 kSrcTonemap3d, // VIG 156 }; 157 158 enum HWToneMapLut { 159 kLutNone, // No valid lut 160 kDma1dIgc, // DMA IGC Lut 161 kDma1dGc, // DMA GC Lut 162 kVig1dIgc, // VIG IGC Lut 163 kVig3dGamut, // 3D Gamut Lut 164 }; 165 166 enum HWWriteOperation { 167 kNoOp, // No-op, previously set config holds good 168 kSet, // Sets the new config 169 kReset, // Resets/Clears the previously set config 170 }; 171 172 enum class HWRecoveryEvent : uint32_t { 173 kSuccess, // driver succeeded recovery 174 kCapture, // driver PP_TIMEOUT, capture logs 175 kDisplayPowerReset, // driver requesting display power cycle 176 }; 177 178 typedef std::map<HWSubBlockType, std::vector<LayerBufferFormat>> FormatsMap; 179 typedef std::map<LayerBufferFormat, float> CompRatioMap; 180 181 // Base Postprocessing features information. 182 class PPFeatureInfo { 183 public: 184 uint32_t enable_flags_ = 0; // bitmap to indicate subset of parameters enabling or not. 185 uint32_t feature_version_ = 0; 186 uint32_t feature_id_ = 0; 187 uint32_t disp_id_ = 0; 188 uint32_t pipe_id_ = 0; 189 ~PPFeatureInfo()190 virtual ~PPFeatureInfo() {} 191 virtual void *GetConfigData(void) const = 0; 192 }; 193 194 struct HWDynBwLimitInfo { 195 uint32_t cur_mode = kBwDefault; 196 uint64_t total_bw_limit[kBwModeMax] = { 0 }; 197 uint64_t pipe_bw_limit[kBwModeMax] = { 0 }; 198 }; 199 200 struct HWPipeCaps { 201 PipeType type = kPipeTypeUnused; 202 uint32_t id = 0; 203 uint32_t master_pipe_id = 0; 204 uint32_t max_rects = 1; 205 bool inverse_pma = 0; 206 uint32_t dgm_csc_version = 0; 207 std::map<HWToneMapLut, uint32_t> tm_lut_version_map = {}; 208 bool block_sec_ui = false; 209 }; 210 211 struct HWRotatorInfo { 212 enum { ROT_TYPE_MDSS, ROT_TYPE_V4L2 }; 213 uint32_t type = ROT_TYPE_MDSS; 214 uint32_t num_rotator = 0; 215 bool has_downscale = false; 216 std::string device_path = ""; 217 float min_downscale = 2.0f; 218 bool downscale_compression = false; 219 uint64_t max_line_width = 0; 220 }; 221 222 enum HWQseedStepVersion { 223 kQseed3v2, 224 kQseed3v3, 225 kQseed3v4, 226 kQseed3litev4, 227 kQseed3litev5, 228 }; 229 230 struct HWDestScalarInfo { 231 uint32_t count = 0; 232 uint32_t max_input_width = 0; 233 uint32_t max_output_width = 0; 234 uint32_t max_scale_up = 1; 235 uint32_t prefill_lines = 4; 236 }; 237 238 enum SmartDMARevision { 239 V1, 240 V2, 241 V2p5 242 }; 243 244 enum InlineRotationVersion { 245 kInlineRotationNone, 246 kInlineRotationV1, 247 kInlineRotationV1p1, 248 }; 249 250 struct HWResourceInfo { 251 uint32_t hw_version = 0; 252 uint32_t hw_revision = 0; 253 uint32_t num_dma_pipe = 0; 254 uint32_t num_vig_pipe = 0; 255 uint32_t num_rgb_pipe = 0; 256 uint32_t num_cursor_pipe = 0; 257 uint32_t num_blending_stages = 0; 258 uint32_t num_solidfill_stages = 0; 259 uint32_t num_control = 0; 260 uint32_t num_mixer_to_disp = 0; 261 uint32_t smp_total = 0; 262 uint32_t smp_size = 0; 263 uint32_t num_smp_per_pipe = 0; 264 uint32_t max_scale_up = 1; 265 uint32_t max_scale_down = 1; 266 uint64_t max_bandwidth_low = 0; 267 uint64_t max_bandwidth_high = 0; 268 uint32_t max_mixer_width = 2048; 269 uint32_t max_pipe_width = 2048; 270 uint32_t max_scaler_pipe_width = 2560; 271 uint32_t max_cursor_size = 0; 272 uint64_t max_pipe_bw = 0; 273 uint32_t max_sde_clk = 0; 274 float clk_fudge_factor = 1.0f; 275 uint32_t macrotile_nv12_factor = 0; 276 uint32_t macrotile_factor = 0; 277 uint32_t linear_factor = 0; 278 uint32_t scale_factor = 0; 279 uint32_t extra_fudge_factor = 0; 280 uint32_t amortizable_threshold = 0; 281 uint32_t system_overhead_lines = 0; 282 bool has_bwc = false; 283 bool has_ubwc = false; 284 bool has_decimation = false; 285 bool has_macrotile = false; 286 bool has_non_scalar_rgb = false; 287 bool is_src_split = false; 288 bool has_dyn_bw_support = false; 289 bool separate_rotator = false; 290 bool has_qseed3 = false; 291 bool has_concurrent_writeback = false; 292 bool has_ppp = false; 293 bool has_excl_rect = false; 294 uint32_t writeback_index = kHWBlockMax; 295 HWDynBwLimitInfo dyn_bw_info; 296 std::vector<HWPipeCaps> hw_pipes; 297 FormatsMap supported_formats_map; 298 HWRotatorInfo hw_rot_info; 299 HWDestScalarInfo hw_dest_scalar_info; 300 bool has_avr = false; 301 bool has_hdr = false; 302 SmartDMARevision smart_dma_rev = SmartDMARevision::V1; 303 float ib_fudge_factor = 1.0f; 304 uint32_t undersized_prefill_lines = 0; 305 CompRatioMap comp_ratio_rt_map; 306 CompRatioMap comp_ratio_nrt_map; 307 uint32_t cache_size = 0; // cache size in bytes 308 HWQseedStepVersion pipe_qseed3_version = kQseed3v2; // only valid when has_qseed3=true 309 uint32_t min_prefill_lines = 0; 310 InlineRotationVersion inrot_version = kInlineRotationNone; 311 std::bitset<32> src_tone_map = 0; //!< Stores the bit mask of src tone map capability 312 int secure_disp_blend_stage = -1; 313 uint32_t num_mnocports = 2; 314 uint32_t mnoc_bus_width = 32; 315 }; 316 317 struct HWSplitInfo { 318 uint32_t left_split = 0; 319 uint32_t right_split = 0; 320 321 bool operator !=(const HWSplitInfo &split_info) { 322 return ((left_split != split_info.left_split) || (right_split != split_info.right_split)); 323 } 324 325 bool operator ==(const HWSplitInfo &split_info) { 326 return !(operator !=(split_info)); 327 } 328 }; 329 330 enum HWS3DMode { 331 kS3DModeNone, 332 kS3DModeLR, 333 kS3DModeRL, 334 kS3DModeTB, 335 kS3DModeFP, 336 kS3DModeMax, 337 }; 338 339 struct HWColorPrimaries { 340 uint32_t white_point[2] = {}; // White point 341 uint32_t red[2] = {}; // Red color primary 342 uint32_t green[2] = {}; // Green color primary 343 uint32_t blue[2] = {}; // Blue color primary 344 }; 345 346 struct HWPanelOrientation { 347 bool rotation = false; 348 bool flip_horizontal = false; 349 bool flip_vertical = false; 350 }; 351 352 struct HWPanelInfo { 353 DisplayPort port = kPortDefault; // Display port 354 HWDisplayMode mode = kModeDefault; // Display mode 355 bool partial_update = false; // Partial update feature 356 int left_align = 1; // ROI left alignment restriction 357 int width_align = 1; // ROI width alignment restriction 358 int top_align = 1; // ROI top alignment restriction 359 int height_align = 1; // ROI height alignment restriction 360 int min_roi_width = 1; // Min width needed for ROI 361 int min_roi_height = 1; // Min height needed for ROI 362 bool needs_roi_merge = false; // Merge ROI's of both the DSI's 363 bool dynamic_fps = false; // Panel Supports dynamic fps 364 bool dfps_porch_mode = false; // dynamic fps VFP or HFP mode 365 bool ping_pong_split = false; // Supports Ping pong split 366 uint32_t min_fps = 0; // Min fps supported by panel 367 uint32_t max_fps = 0; // Max fps supported by panel 368 bool is_primary_panel = false; // Panel is primary display 369 bool is_pluggable = false; // Panel is pluggable 370 HWSplitInfo split_info; // Panel split configuration 371 char panel_name[256] = {0}; // Panel name 372 HWS3DMode s3d_mode = kS3DModeNone; // Panel's current s3d mode. 373 int panel_max_brightness = 0; // Max panel brightness 374 uint32_t left_roi_count = 1; // Number if ROI supported on left panel 375 uint32_t right_roi_count = 1; // Number if ROI supported on right panel 376 bool hdr_enabled = false; // HDR feature supported 377 bool hdr_metadata_type_one = false; // Static HDR metadata type one 378 uint32_t hdr_eotf = 0; // Electro optical transfer function 379 float peak_luminance = 0.0f; // Panel's peak luminance level 380 float average_luminance = 0.0f; // Panel's average luminance level 381 float blackness_level = 0.0f; // Panel's blackness level 382 HWColorPrimaries primaries = {}; // WRGB color primaries 383 HWPanelOrientation panel_orientation = {}; // Panel Orientation 384 uint32_t transfer_time_us = 0; // transfer time in micro seconds to panel's active region 385 bool qsync_support = false; // Specifies panel supports qsync feature or not. 386 bool dyn_bitclk_support = false; // Bit clk can be updated to avoid RF interference. 387 std::vector<uint64_t> bitclk_rates; // Supported bit clk levels. 388 389 bool operator !=(const HWPanelInfo &panel_info) { 390 return ((port != panel_info.port) || (mode != panel_info.mode) || 391 (partial_update != panel_info.partial_update) || 392 (left_align != panel_info.left_align) || (width_align != panel_info.width_align) || 393 (top_align != panel_info.top_align) || (height_align != panel_info.height_align) || 394 (min_roi_width != panel_info.min_roi_width) || 395 (min_roi_height != panel_info.min_roi_height) || 396 (needs_roi_merge != panel_info.needs_roi_merge) || 397 (dynamic_fps != panel_info.dynamic_fps) || (min_fps != panel_info.min_fps) || 398 (dfps_porch_mode != panel_info.dfps_porch_mode) || 399 (ping_pong_split != panel_info.ping_pong_split) || 400 (max_fps != panel_info.max_fps) || (is_primary_panel != panel_info.is_primary_panel) || 401 (split_info != panel_info.split_info) || (s3d_mode != panel_info.s3d_mode) || 402 (left_roi_count != panel_info.left_roi_count) || 403 (right_roi_count != panel_info.right_roi_count) || 404 (transfer_time_us != panel_info.transfer_time_us) || 405 (qsync_support != panel_info.qsync_support) || 406 (dyn_bitclk_support != panel_info.dyn_bitclk_support) || 407 (bitclk_rates != panel_info.bitclk_rates)); 408 } 409 410 bool operator ==(const HWPanelInfo &panel_info) { 411 return !(operator !=(panel_info)); 412 } 413 }; 414 415 struct HWSessionConfig { 416 LayerRect src_rect {}; 417 LayerRect dst_rect {}; 418 uint32_t buffer_count = 0; 419 bool secure = false; 420 uint32_t frame_rate = 0; 421 LayerTransform transform; 422 bool secure_camera = false; 423 424 bool operator==(const HWSessionConfig& config) const { 425 return (src_rect == config.src_rect && 426 dst_rect == config.dst_rect && 427 buffer_count == config.buffer_count && 428 secure == config.secure && 429 frame_rate == config.frame_rate && 430 transform == config.transform && 431 secure_camera == config.secure_camera); 432 } 433 434 bool operator!=(const HWSessionConfig& config) const { 435 return !operator==(config); 436 } 437 }; 438 439 enum HWRotatorMode { 440 kRotatorNone, 441 kRotatorOffline, 442 kRotatorInline 443 }; 444 445 struct HWRotateInfo { 446 int pipe_id = -1; // Not actual pipe id, but the relative DMA id 447 int writeback_id = -1; // Writeback block id, but this is the same as DMA id 448 LayerRect src_roi {}; // Source crop of each split 449 LayerRect dst_roi {}; // Destination crop of each split 450 bool valid = false; 451 int rotate_id = -1; // Actual rotator session id with driver 452 }; 453 454 struct HWRotatorSession { 455 HWRotateInfo hw_rotate_info[kMaxRotatePerLayer] {}; 456 uint32_t hw_block_count = 0; // number of rotator hw blocks used by rotator session 457 int session_id = -1; // A handle with Session Manager 458 HWSessionConfig hw_session_config {}; 459 LayerBuffer input_buffer {}; // Input to rotator 460 LayerBuffer output_buffer {}; // Output of rotator, crop width and stride are same 461 float input_compression = 1.0f; 462 float output_compression = 1.0f; 463 bool is_buffer_cached = false; 464 HWRotatorMode mode = kRotatorNone; 465 }; 466 467 struct HWScaleLutInfo { 468 uint32_t dir_lut_size = 0; 469 uint32_t cir_lut_size = 0; 470 uint32_t sep_lut_size = 0; 471 uint64_t dir_lut = 0; 472 uint64_t cir_lut = 0; 473 uint64_t sep_lut = 0; 474 }; 475 476 struct HWDetailEnhanceData : DisplayDetailEnhancerData { 477 uint16_t prec_shift = 0; 478 int16_t adjust_a[MAX_DETAIL_ENHANCE_CURVE] = {0}; 479 int16_t adjust_b[MAX_DETAIL_ENHANCE_CURVE] = {0}; 480 int16_t adjust_c[MAX_DETAIL_ENHANCE_CURVE] = {0}; 481 }; 482 483 struct HWPixelExtension { 484 int32_t extension = 0; // Number of pixels extension in left, right, top and bottom directions 485 // for all color components. This pixel value for each color component 486 // should be sum of fetch and repeat pixels. 487 488 int32_t overfetch = 0; // Number of pixels need to be overfetched in left, right, top and bottom 489 // directions from source image for scaling. 490 491 int32_t repeat = 0; // Number of pixels need to be repeated in left, right, top and bottom 492 // directions for scaling. 493 }; 494 495 struct HWPlane { 496 int32_t init_phase_x = 0; 497 int32_t phase_step_x = 0; 498 int32_t init_phase_y = 0; 499 int32_t phase_step_y = 0; 500 HWPixelExtension left {}; 501 HWPixelExtension top {}; 502 HWPixelExtension right {}; 503 HWPixelExtension bottom {}; 504 uint32_t roi_width = 0; 505 int32_t preload_x = 0; 506 int32_t preload_y = 0; 507 uint32_t src_width = 0; 508 uint32_t src_height = 0; 509 }; 510 511 struct HWCsc { 512 int64_t ctm_coeff[MAX_CSC_MATRIX_COEFF_SIZE] = {0}; 513 uint32_t pre_bias[MAX_CSC_BIAS_SIZE] = {0}; 514 uint32_t post_bias[MAX_CSC_BIAS_SIZE] = {0}; 515 uint32_t pre_clamp[MAX_CSC_CLAMP_SIZE] = {0}; 516 uint32_t post_clamp[MAX_CSC_CLAMP_SIZE] = {0}; 517 }; 518 519 struct HWScaleData { 520 struct enable { 521 uint8_t scale = 0; 522 uint8_t direction_detection = 0; 523 uint8_t detail_enhance = 0; 524 } enable; 525 uint32_t dst_width = 0; 526 uint32_t dst_height = 0; 527 uint32_t dir_weight = 0; 528 HWPlane plane[MAX_PLANES] {}; 529 // scale_v2_data fields 530 ScalingFilterConfig y_rgb_filter_cfg = kFilterEdgeDirected; 531 ScalingFilterConfig uv_filter_cfg = kFilterEdgeDirected; 532 HWAlphaInterpolation alpha_filter_cfg = kInterpolationPixelRepeat; 533 HWBlendingFilter blend_cfg = kBlendFilterCircular; 534 535 struct lut_flags { 536 uint8_t lut_swap = 0; 537 uint8_t lut_dir_wr = 0; 538 uint8_t lut_y_cir_wr = 0; 539 uint8_t lut_uv_cir_wr = 0; 540 uint8_t lut_y_sep_wr = 0; 541 uint8_t lut_uv_sep_wr = 0; 542 } lut_flag; 543 544 uint32_t dir_lut_idx = 0; 545 /* for Y(RGB) and UV planes*/ 546 uint32_t y_rgb_cir_lut_idx = 0; 547 uint32_t uv_cir_lut_idx = 0; 548 uint32_t y_rgb_sep_lut_idx = 0; 549 uint32_t uv_sep_lut_idx = 0; 550 HWDetailEnhanceData detail_enhance {}; 551 }; 552 553 struct HWDestScaleInfo { 554 uint32_t mixer_width = 0; 555 uint32_t mixer_height = 0; 556 bool scale_update = false; 557 HWScaleData scale_data = {}; 558 LayerRect panel_roi = {}; 559 }; 560 561 typedef std::map<uint32_t, HWDestScaleInfo *> DestScaleInfoMap; 562 563 struct HWAVRInfo { 564 bool enable = false; // Flag to Enable AVR feature 565 HWAVRModes mode = kContinuousMode; // Specifies the AVR mode 566 }; 567 568 struct HWPipeCscInfo { 569 HWWriteOperation op = kNoOp; 570 HWCsc csc = {}; 571 }; 572 573 struct HWPipeTonemapLutInfo { 574 HWWriteOperation op = kNoOp; 575 HWToneMapLut type = kLutNone; 576 std::shared_ptr<PPFeatureInfo> pay_load = nullptr; 577 }; 578 579 struct HWPipeTonemapInversePma { 580 HWWriteOperation op = kNoOp; 581 bool inverse_pma = false; 582 }; 583 584 struct HWPipeInfo { 585 HWPipeInfo *pair = NULL; 586 uint8_t rect = 255; 587 uint32_t pipe_id = 0; 588 HWSubBlockType sub_block_type = kHWSubBlockMax; 589 LayerRect src_roi {}; 590 LayerRect dst_roi {}; 591 LayerRect excl_rect {}; // exclusion rectangle per pipe rectangle 592 uint8_t horizontal_decimation = 0; 593 uint8_t vertical_decimation = 0; 594 HWScaleData scale_data {}; 595 uint32_t z_order = 0; 596 uint32_t flags = 0; 597 bool valid = false; 598 bool is_virtual = 0; 599 HWPipeTonemapInversePma inverse_pma_info = {}; 600 HWPipeCscInfo dgm_csc_info = {}; 601 std::vector<HWPipeTonemapLutInfo> lut_info = {}; 602 HWSrcTonemap tonemap = kSrcTonemapNone; 603 }; 604 605 struct HWSolidfillStage { 606 uint32_t z_order = kMaxSDELayers; 607 uint32_t color = 0; 608 LayerRect roi = {}; 609 bool is_exclusion_rect = false; 610 LayerSolidFill solid_fill_info = {}; 611 }; 612 613 struct HWLayerConfig { 614 HWPipeInfo left_pipe {}; // pipe for left side of output 615 HWPipeInfo right_pipe {}; // pipe for right side of output 616 HWRotatorSession hw_rotator_session {}; 617 HWSolidfillStage hw_solidfill_stage {}; 618 float compression = 1.0f; 619 bool use_solidfill_stage = false; 620 }; 621 622 struct HWHDRLayerInfo { 623 enum HDROperation { 624 kNoOp, // No-op. 625 kSet, // Sets the HDR MetaData - Start of HDR 626 kReset, // resets the previously set HDR Metadata, End of HDR 627 }; 628 629 int32_t layer_index = -1; 630 HDROperation operation = kNoOp; 631 }; 632 633 struct LayerExt { 634 std::vector<LayerRect> excl_rects = {}; // list of exclusion rects 635 }; 636 637 struct HWLayersInfo { 638 LayerStack *stack = NULL; // Input layer stack. Set by the caller. 639 uint32_t app_layer_count = 0; // Total number of app layers. Must not be 0. 640 uint32_t gpu_target_index = 0; // GPU target layer index. 0 if not present. 641 std::vector<ColorPrimaries> wide_color_primaries = {}; // list of wide color primaries 642 643 std::vector<Layer> hw_layers = {}; // Layers which need to be programmed on the HW 644 std::vector<LayerExt> layer_exts = {}; // Extention layer having list of 645 // exclusion rectangles for each layer 646 std::vector<uint32_t> index {}; // Indexes of the layers from the layer stack which need to 647 // be programmed on hardware. 648 std::vector<uint32_t> roi_index {}; // Stores the ROI index where the layers are visible. 649 int sync_handle = -1; // Release fence id for current draw cycle. 650 int set_idle_time_ms = -1; // Set idle time to the new specified value. 651 // -1 indicates no change in idle time since last set value. 652 std::vector<LayerRect> left_frame_roi = {}; // Left ROI. 653 std::vector<LayerRect> right_frame_roi = {}; // Right ROI. 654 LayerRect partial_fb_roi = {}; // Damaged area in framebuffer. 655 bool roi_split = false; // Indicates separated left and right ROI 656 bool async_cursor_updates = false; // Cursor layer allowed to have async updates 657 bool fast_path_composition = false; // Indicates frame has fast path composition 658 DestScaleInfoMap dest_scale_info_map = {}; 659 HWHDRLayerInfo hdr_layer_info = {}; 660 Handle pvt_data = NULL; // Private data used by sdm extension only. 661 }; 662 663 struct HWQosData { 664 uint64_t core_ab_bps = 0; 665 uint64_t core_ib_bps = 0; 666 uint64_t llcc_ab_bps = 0; 667 uint64_t llcc_ib_bps = 0; 668 uint64_t dram_ab_bps = 0; 669 uint64_t dram_ib_bps = 0; 670 uint64_t rot_prefill_bw_bps = 0; 671 uint32_t clock_hz = 0; 672 uint32_t rot_clock_hz = 0; 673 }; 674 675 enum UpdateType { 676 kUpdateResources, // Indicates Strategy & RM execution, which can update resources. 677 kUpdateMax, 678 }; 679 680 struct HWLayers { 681 HWLayersInfo info {}; 682 HWLayerConfig config[kMaxSDELayers] {}; 683 float output_compression = 1.0f; 684 HWQosData qos_data = {}; 685 HWAVRInfo hw_avr_info = {}; 686 std::bitset<kUpdateMax> updates_mask = 0; 687 }; 688 689 struct HWDisplayAttributes : DisplayConfigVariableInfo { 690 bool is_device_split = false; 691 uint32_t v_front_porch = 0; //!< Vertical front porch of panel 692 uint32_t v_back_porch = 0; //!< Vertical back porch of panel 693 uint32_t v_pulse_width = 0; //!< Vertical pulse width of panel 694 uint32_t h_total = 0; //!< Total width of panel (hActive + hFP + hBP + hPulseWidth) 695 uint32_t v_total = 0; //!< Total height of panel (vActive + vFP + vBP + vPulseWidth) 696 std::bitset<32> s3d_config {}; //!< Stores the bit mask of S3D modes 697 uint32_t clock_khz = 0; //!< Stores the pixel clock of panel in khz 698 HWTopology topology = kUnknown; //!< Stores the topology information. 699 700 bool operator !=(const HWDisplayAttributes &display_attributes) { 701 return ((is_device_split != display_attributes.is_device_split) || 702 (x_pixels != display_attributes.x_pixels) || 703 (y_pixels != display_attributes.y_pixels) || 704 (x_dpi != display_attributes.x_dpi) || 705 (y_dpi != display_attributes.y_dpi) || 706 (fps != display_attributes.fps) || 707 (vsync_period_ns != display_attributes.vsync_period_ns) || 708 (v_front_porch != display_attributes.v_front_porch) || 709 (v_back_porch != display_attributes.v_back_porch) || 710 (v_pulse_width != display_attributes.v_pulse_width) || 711 (h_total != display_attributes.h_total) || 712 (is_yuv != display_attributes.is_yuv) || 713 (s3d_config != display_attributes.s3d_config) || 714 (clock_khz != display_attributes.clock_khz) || 715 (topology != display_attributes.topology)); 716 } 717 718 bool operator ==(const HWDisplayAttributes &display_attributes) { 719 return !(operator !=(display_attributes)); 720 } 721 OnlyFpsChangedHWDisplayAttributes722 bool OnlyFpsChanged(const HWDisplayAttributes &display_attributes) { 723 return ((fps != display_attributes.fps) && 724 (vsync_period_ns != display_attributes.vsync_period_ns) && 725 (x_pixels == display_attributes.x_pixels) && 726 (y_pixels == display_attributes.y_pixels) && 727 (x_dpi == display_attributes.x_dpi) && 728 (y_dpi == display_attributes.y_dpi) && 729 (topology == display_attributes.topology) && 730 (is_device_split == display_attributes.is_device_split) && 731 (v_front_porch == display_attributes.v_front_porch) && 732 (v_back_porch == display_attributes.v_back_porch) && 733 (v_pulse_width == display_attributes.v_pulse_width) && 734 (h_total == display_attributes.h_total) && 735 (is_yuv == display_attributes.is_yuv) && 736 (s3d_config == display_attributes.s3d_config) && 737 (clock_khz == display_attributes.clock_khz)); 738 } 739 }; 740 741 struct HWMixerAttributes { 742 uint32_t width = 0; // Layer mixer width 743 uint32_t height = 0; // Layer mixer height 744 uint32_t split_left = 0; 745 LayerBufferFormat output_format = kFormatRGB101010; // Layer mixer output format 746 747 bool operator !=(const HWMixerAttributes &mixer_attributes) { 748 return ((width != mixer_attributes.width) || 749 (height != mixer_attributes.height) || 750 (output_format != mixer_attributes.output_format) || 751 (split_left != mixer_attributes.split_left)); 752 } 753 754 bool operator ==(const HWMixerAttributes &mixer_attributes) { 755 return !(operator !=(mixer_attributes)); 756 } 757 IsValidHWMixerAttributes758 bool IsValid() { 759 return (width > 0 && height > 0); 760 } 761 }; 762 763 } // namespace sdm 764 765 #endif // __HW_INFO_TYPES_H__ 766 767