Home
last modified time | relevance | path

Searched refs:Rn (Results 1 – 13 of 13) sorted by relevance

/system/core/libpixelflinger/codeflinger/
DArm64Assembler.cpp340 int s, int Rd, int Rn, uint32_t Op2) in dataProcessingCommon() argument
397 case opADD: *mPC++ = A64_ADD_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
398 case opAND: *mPC++ = A64_AND_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
399 case opORR: *mPC++ = A64_ORR_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
400 case opMVN: *mPC++ = A64_ORN_W(Rd, Rn, Rm, shift, amount); break; in dataProcessingCommon()
401 case opSUB: *mPC++ = A64_SUB_W(Rd, Rn, Rm, shift, amount, s);break; in dataProcessingCommon()
408 int s, int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
419 dataProcessingCommon(opcode, s, Wd, Rn, Op2); in dataProcessing()
423 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2); in dataProcessing()
427 dataProcessingCommon(opSUB, s, Wd, Rn, Op2); in dataProcessing()
[all …]
DARMAssemblerInterface.h124 int Rd, int Rn,
129 int Rd, int Rm, int Rs, int Rn) = 0;
144 virtual void BX(int cc, int Rn) = 0;
155 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
157 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
159 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
161 int Rn, uint32_t offset = __immed12_pre(0)) = 0;
164 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
166 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
168 int Rn, uint32_t offset = __immed8_pre(0)) = 0;
[all …]
DARMAssemblerProxy.cpp161 int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2); in dataProcessing()
166 void ARMAssemblerProxy::MLA(int cc, int s, int Rd, int Rm, int Rs, int Rn) { in MLA() argument
167 mTarget->MLA(cc, s, Rd, Rm, Rs, Rn); in MLA()
195 void ARMAssemblerProxy::BX(int cc, int Rn) { in BX() argument
196 mTarget->BX(cc, Rn); in BX()
212 void ARMAssemblerProxy::LDR(int cc, int Rd, int Rn, uint32_t offset) { in LDR() argument
213 mTarget->LDR(cc, Rd, Rn, offset); in LDR()
215 void ARMAssemblerProxy::LDRB(int cc, int Rd, int Rn, uint32_t offset) { in LDRB() argument
216 mTarget->LDRB(cc, Rd, Rn, offset); in LDRB()
[all …]
DArm64Assembler.h99 int Rd, int Rn,
102 int Rd, int Rm, int Rs, int Rn);
116 virtual void BX(int cc, int Rn);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t Op2);
128 int Rn, uint32_t Op2);
130 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0);
135 int Rn, uint32_t offset = 0);
137 int Rn, uint32_t offset = 0);
[all …]
DARMAssemblerProxy.h80 int Rd, int Rn,
83 int Rd, int Rm, int Rs, int Rn);
97 virtual void BX(int cc, int Rn);
105 int Rn, uint32_t offset = __immed12_pre(0));
107 int Rn, uint32_t offset = __immed12_pre(0));
109 int Rn, uint32_t offset = __immed12_pre(0));
111 int Rn, uint32_t offset = __immed12_pre(0));
113 int Rn, uint32_t offset = __immed8_pre(0));
115 int Rn, uint32_t offset = __immed8_pre(0));
117 int Rn, uint32_t offset = __immed8_pre(0));
[all …]
DMIPS64Assembler.cpp392 int s, int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
408 mMips->AND(Rd, Rn, src); in dataProcessing()
410 mMips->ANDI(Rd, Rn, src); in dataProcessing()
417 mMips->ADDU(Rd, Rn, src); in dataProcessing()
419 mMips->ADDIU(Rd, Rn, src); in dataProcessing()
426 mMips->SUBU(Rd, Rn, src); in dataProcessing()
428 mMips->SUBIU(Rd, Rn, src); in dataProcessing()
435 mMips->DADDU(Rd, Rn, src); in dataProcessing()
437 mMips->DADDIU(Rd, Rn, src); in dataProcessing()
444 mMips->DSUBU(Rd, Rn, src); in dataProcessing()
[all …]
DARMAssembler.h91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = __immed12_pre(0));
118 int Rn, uint32_t offset = __immed12_pre(0));
120 int Rn, uint32_t offset = __immed12_pre(0));
122 int Rn, uint32_t offset = __immed12_pre(0));
124 int Rn, uint32_t offset = __immed8_pre(0));
126 int Rn, uint32_t offset = __immed8_pre(0));
128 int Rn, uint32_t offset = __immed8_pre(0));
[all …]
DARMAssembler.cpp203 int s, int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
205 *mPC++ = (cc<<28) | (opcode<<21) | (s<<20) | (Rn<<16) | (Rd<<12) | Op2; in dataProcessing()
215 int Rd, int Rm, int Rs, int Rn) { in MLA() argument
217 LOG_FATAL_IF(Rd==Rm, "MLA(r%u,r%u,r%u,r%u)", Rd,Rm,Rs,Rn); in MLA()
219 (Rd<<16) | (Rn<<12) | (Rs<<8) | 0x90 | Rm; in MLA()
274 void ARMAssembler::BX(int cc, int Rn) in BX() argument
276 *mPC++ = (cc<<28) | 0x12FFF10 | Rn; in BX()
285 void ARMAssembler::LDR(int cc, int Rd, int Rn, uint32_t offset) { in LDR() argument
286 *mPC++ = (cc<<28) | (1<<26) | (1<<20) | (Rn<<16) | (Rd<<12) | offset; in LDR()
288 void ARMAssembler::LDRB(int cc, int Rd, int Rn, uint32_t offset) { in LDRB() argument
[all …]
DARMAssemblerInterface.cpp70 int Rn, uint32_t offset) in ADDR_LDR() argument
72 LDR(cc, Rd, Rn, offset); in ADDR_LDR()
75 int Rn, uint32_t offset) in ADDR_STR() argument
77 STR(cc, Rd, Rn, offset); in ADDR_STR()
80 int Rd, int Rn, uint32_t Op2) in ADDR_ADD() argument
82 dataProcessing(opADD, cc, s, Rd, Rn, Op2); in ADDR_ADD()
85 int Rd, int Rn, uint32_t Op2) in ADDR_SUB() argument
87 dataProcessing(opSUB, cc, s, Rd, Rn, Op2); in ADDR_SUB()
DMIPS64Assembler.h96 int Rd, int Rn,
99 int Rd, int Rm, int Rs, int Rn);
113 virtual void BX(int cc, int Rn);
121 int Rn, uint32_t offset = 0);
123 int Rn, uint32_t offset = 0);
125 int Rn, uint32_t offset = 0);
127 int Rn, uint32_t offset = 0);
129 int Rn, uint32_t offset = 0);
131 int Rn, uint32_t offset = 0);
133 int Rn, uint32_t offset = 0);
[all …]
DMIPSAssembler.cpp412 int s, int Rd, int Rn, uint32_t Op2) in dataProcessing() argument
429 mMips->AND(Rd, Rn, src); in dataProcessing()
431 mMips->ANDI(Rd, Rn, src); in dataProcessing()
438 mMips->ADDU(Rd, Rn, src); in dataProcessing()
440 mMips->ADDIU(Rd, Rn, src); in dataProcessing()
447 mMips->SUBU(Rd, Rn, src); in dataProcessing()
449 mMips->SUBIU(Rd, Rn, src); in dataProcessing()
455 mMips->XOR(Rd, Rn, src); in dataProcessing()
457 mMips->XORI(Rd, Rn, src); in dataProcessing()
463 mMips->OR(Rd, Rn, src); in dataProcessing()
[all …]
DMIPSAssembler.h91 int Rd, int Rn,
94 int Rd, int Rm, int Rs, int Rn);
108 virtual void BX(int cc, int Rn);
116 int Rn, uint32_t offset = 0);
118 int Rn, uint32_t offset = 0);
120 int Rn, uint32_t offset = 0);
122 int Rn, uint32_t offset = 0);
124 int Rn, uint32_t offset = 0);
126 int Rn, uint32_t offset = 0);
128 int Rn, uint32_t offset = 0);
[all …]
/system/core/libpixelflinger/tests/arch-arm64/assembler/
Darm64_assembler_test.cpp414 uint32_t Rn = 1, uint32_t Rm = 2, uint32_t Rs = 3) in dataOpTest() argument
428 regs[Rn] = test.RnValue; in dataOpTest()
449 case INSTR_ADD: a64asm->ADD(test.cond, test.setFlags, Rd,Rn,op2); break; in dataOpTest()
450 case INSTR_SUB: a64asm->SUB(test.cond, test.setFlags, Rd,Rn,op2); break; in dataOpTest()
451 case INSTR_RSB: a64asm->RSB(test.cond, test.setFlags, Rd,Rn,op2); break; in dataOpTest()
452 case INSTR_AND: a64asm->AND(test.cond, test.setFlags, Rd,Rn,op2); break; in dataOpTest()
453 case INSTR_ORR: a64asm->ORR(test.cond, test.setFlags, Rd,Rn,op2); break; in dataOpTest()
454 case INSTR_BIC: a64asm->BIC(test.cond, test.setFlags, Rd,Rn,op2); break; in dataOpTest()
456 case INSTR_MLA: a64asm->MLA(test.cond, test.setFlags, Rd,Rm,Rs,Rn); break; in dataOpTest()
457 case INSTR_CMP: a64asm->CMP(test.cond, Rn,op2); break; in dataOpTest()
[all …]