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3%s: Enable clock %s failed
3%s: resmgr not allocated
3%s: Cannot turn on MCLK, BG is not enabled
%s: marking ready completion
3%s: Invalid handle to device
audio_ext_clk_get_parent [STATE_IDLE] disable STATE_LO 3%s: Disable clock %s failed
4%s: RCO enable requires MCLK to be ON first
3%s: init extclk fail: %d
qcom,img-filename %s: Failed, err = %d for base_addr = 0x%x split_fname = %s, load_addr = 0x%x, size = 0x%zx
wdsp qcom,codec-ext-clk-src /buildbot/src/partner-android/q-dev-msm-floral-4.14-qt-qpr3/private/msm-google/techpack/audio/asoc/codecs/audio-ext-clk-up.c audio_lpass_mclk6 /buildbot/src/partner-android/q-dev-msm-floral-4.14-qt-qpr3/private/msm-google/techpack/audio/asoc/codecs/wcd-clsh.c wcd_resmgr_disable_clk_block wcd_cal_create_hwdep &wdsp->ssr_mutex %s: mutex_lock(%s)
wdsp_collect_ramdumps wdsp->api_mutex wdsp_signal_handler wdsp_ssr_handler lpass_hw_vote_clk %s: parent index = %u
lpass_hw_vote_unprepare [ wcd_clsh_imped_config wcd_clsh_state_lo %s: LO cannot be in this mode: %d
wcd_resmgr_get_clk_type wcd_resmgr_enable_master_bias WCD_CLK_OFF %s: new hwdep failed %d
%s: Init failed (%d) for component %s
%s: Failed WDSP shutdown, err = %d
__wdsp_clr_ready_locked %s: component %s failed to suspend
audio_ext_clk_unprepare lpass_hw_vote_prepare %s: miss mclk reg
CLS_H_NORMAL wcd_clsh_state_ear_aux wcd_clsh_state_hph_lo wcd_resmgr_post_ssr_v2 3%s: wrong arguments passed
wdsp_is_valid_elf_hdr 3%s: no segments to load
qcom,wdsp-components %s: Property %s not defined in DT
WDSP_DOWN wdsp_debug_dump_handler %s: Invalid input, arg is NULL
%s: ext-clk freq: %d, lpass clk_id: %d, clk_src: %d
active qcom,mclk-clk-reg wcd_clsh_state_err wcd_clsh_state_hph_aux %s: hph_mode = %d
%s: current master bias users: %d
wcd_resmgr_codec_reg_update_bits WCD_CLK_UNDEFINED %s.b%02d %s: Failed to add master, err = %d
wdsp_init_components wdsp_vote_for_dsp wcd_clsh_set_hph_mode %s: buck_users %d, enable %d, mode: %s &resmgr->codec_bg_clk_lock wdsp_get_cmpnt_type_string wdsp_mgr_bind wdsp_disable_dsp audio_get_clk_data wcd_clsh_state_hph_r &fw_data->lock 3%s: init dsp mgr fail: %d
&wdsp->api_mutex wdsp_load_each_segment pmic-clock-names %s: Class-H not a valid new state: %s
wcd_clsh_state_hph_ear wcd_resmgr_enable_clk_block Codec %s wdsp_get_segment_list /buildbot/src/partner-android/q-dev-msm-floral-4.14-qt-qpr3/private/msm-google/techpack/audio/asoc/codecs/wcd-dsp-mgr.c ipc %s: cannot dump memory, ssr_type %s, dumps %s
%s: wdsp %s failed, err = %d
wdsp_enable_dsp audio_ref_clk_probe %s: clk_init is failed
3%s: rco_clk_users = %d, clk_type = %d, cannot disable
%s: cmpnt %d already added
%s: Error %d to download code sections
%s: Ramdump device is not setup
pm6125_div_clk1 wcd_clsh_flyback_ctrl wcd_clsh_state_hph_l wcd_resmgr_set_sido_input_src qcom,codec-lpass-clk-id qpnp_clkdiv_1 audio_get_pinctrl STATE_EAR CLS_H_HIFI wcd_resmgr_init 3%s: wrong ioctl command sent %d!
%s: component not found at idx %d
3%s: Invalid ssr_type %d
%s: Current ssr_type %s, handling ssr_type %s
3%s lpass core hw vote failed %d
] CLS_AB_HIFI %s: Normal mode not applicable for hph_r
%s: clear 0x%lx, new_state = 0x%x
CDC_UP qcom,codec-lpass-ext-clk-freq 3%s: Cannot get wcd9xx pointer
wcd_resmgr_disable_clk_mclk wdsp_download_segments ln_bb_clk3 wcd_clsh_state_aux %s: clsh_users %d, enable %d %s: native_clk %x rx1_rate= %x rx2_rate= %x wcd_clsh_state_ear_lo %s: mclk_users: %d, clk_type: %s
3%s: Invalid private_data
%s: dload code sections failed, err = %d
%s: Failed to register component dev %s
%s: Data section download failed, err = %d
%s Wrong request for class H state machine requested to %s %s
wcd_clsh_state_hph_st %s, impedance not in range = %d
%s: flyback_users %d, enable %d, mode: %s 3%s: wrong ioctl command sent %u!
wcdcal_hwdep_ioctl_compat Invalid audio-ref-clk %s: could not get sleep pinstate
%s: Class-H already in requested state: %s
CLS_H_LP mbhc 3%s: wrong cal type sent %d
%s: Invalid input params
%s: set 0x%lx, new_state = 0x%x
wdsp_ssr_work_fn NO_SSR wdsp_get_devops_for_cmpnt %s: Failed to boot dsp, err = %d
3%s: afe_set_lpass_clk_cfg failed, ret = %d
sleep %s:Invalid mode %d
wcd_clsh_fsm %s, detected impedance is greater than 12 Ohm
%s: mode: %s cannot be used for EAR
Buffer overflow detected (%d < %lu)!
3%s: Firmware too small
3%s: Too small MDT file
%s: %s size mismatch, phdr_size: 0x%x fw_size: 0x%zx enabled audio_lpass_mclk 3%s afe_set_digital_codec_core_clock failed
%s: could not get active pinstate
%s: clock register failed for clk_src = %d\n %s: clock add failed for clk_src = %d
get_impedance_index %s: Acquiring BG_CLK done
3%s: incorrect firmware size %d for %s
%s: firmware %s not found
%s: component_bind_all failed %d
%s: Raised signal %d
wdsp_mgr audio_lpass_mclk2 STATE_HPH_R %s: flyback_users %d, enable %d, mode: %s
%s: buck_users %d, enable %d, mode: %s
wcd_resmgr_enable_clk_mclk WCD_CLK_MCLK wcdcal_get_fw_cal wcd-dsp-mgr wdsp_mgr_probe %s: Invalid phandle + arg count %d, expected %d
%s: INIT failed, err = %d
%s: Invalid type %u
%s: do_ramdump failed with error %d
STATE_AUX CLS_H_INVALID wcd_resmgr_codec_reg_read wdsp_mgr_parse_phandle %s: Error %d to get image segments for type %d
%s: mutex_unlock(%s)
wdsp_get_ssr_type_string %s: handling signal %d failed with error %d
%s ioremap failed
CLS_H_LOHIFI wcdcal_hwdep_ioctl 3%s: Not an ELF file
%s: Reading property %s failed, error = %d
%s: parse_phandle at index %d failed %d
%s: invalid phandle_arg to of_node %s
%s: create_ramdump_device failed
%s: SSR handling is running, skip debug ramdump
%s: WDSP in invalid state 0x%x
%s: could not get clk source, ret = %d
%s: use-pinctrl : %d
%s: Normal mode not applicable for hph_l
wcd_resmgr_set_sido_input_src_locked 3%s: Error enabling MCLK, clk_type: %s
3%s: cal not sent by userspace %d
%s: base_addr 0x%x, split_fname %s, load_addr 0x%x, size 0x%zx
%s: %s did not register ops
audio_ext_clk_prepare %s: already requested before
wcd9xxx_dlkm STATE_HPH_L %s: Releasing BG_CLK
%s: sido input src to internal
WCD_CLK_RCO anc %s: fw mdt %s is invalid
wdsp_add_segment_to_list wdsp_mgr_parse_dt_entries 3%s: Invalid component type %d
%s: Invalid start addr 0x%x or dump_size 0x%zx
CDC_DOWN %s: undefined ssr_type %d
__wdsp_dbg_dump_locked LPASS_HW_MACRO CLS_AB is_native_44_1_active /buildbot/src/partner-android/q-dev-msm-floral-4.14-qt-qpr3/private/msm-google/techpack/audio/asoc/codecs/wcd9xxx-resmgr-v2.c wcd_resmgr_enable_clk_rco 3%s: failed to copy
wcd9xxx_soc_init wdsp_init_and_dload_code_sections %s: request %s, current users = %d
%s: Invalid clk source = %d
3%s: active state select failed with %d
| enable %s: mode: %s, %s
&resmgr->master_bias_lock 3%s: codec/regmap not defined
%s: rco clk users: %d, clk_type: %s
disabled audio_lpass_mclk4 CLS_H_ULP /buildbot/src/partner-android/q-dev-msm-floral-4.14-qt-qpr3/private/msm-google/techpack/audio/asoc/codecs/wcd9xxx-common-v2.c %s Wrong request for class H state machine requested to %s %s %s: Acquiring BG_CLK
3%s: Unknown Clock type: %s
3%s: Codec memory is NULL, nothing to post init
wcdcal_hwdep_ioctl_shared control %s: Invalid addr 0x%x, base_addr = 0x%x
%s: wdsp in invalid state 0x%x
wdsp_suspend audio_ext_pmi_clk audio_lpass_mclk3 %s: Unable to get pinctrl handle
%s: Disable TLMM pins failed with %d
%s: ClassH state transition from %s to %s
3%s: resmgr not initialized
3%s: No mclk users, cannot disable mclk
3%s: fw_data is NULL
3%s: Invalid device handle
%s.mdt ELF qcom,wdsp-cmpnt-dev-name wdsp_load_fw_image %s: not valid event_handler for %s
%s: wait_for_ready timed out, status = 0x%x
%s: Failed to dload code sections err = %d
&x->wait wdsp_register_cmpnt_ops %s: ready_status = 0x%x
__wdsp_set_ready_locked qcom,use-pinctrl %s: Parsing PMI pinctrl failed
audio_ext_pmi_lnbb_clk audio_lpass_mclk5 %s:Invalid old state:%s
[STATE_UNKNOWN] wcd_resmgr_disable_clk_rco %s: Failed to read dumps, size 0x%zx at addr 0x%x
%s: Failed to shutdown dsp, err = %d
%s: component %s failed to resume
panic_on_error %s: selected impedance index = %d
%s: sido input src to external
wcd_resmgr_post_init vbat %s: no memory for %s cal
%s: Invalid request for segment_type %d
wdsp_unicast_event wdsp_resume audio_lpass_mclk7 pms405_div_clk1 pm6150_div_clk1 wcd_clsh_state_ear wcd_clsh_buck_ctrl %s, detected impedance is less than 4 Ohm
%s:clsh is already enabled
RCO Calibration failed
mad 3%s: Not an executable image
wdsp->ssr_mutex %s: base_addr 0x%x, dump_start_addr 0x%x, dump_size 0x%zx
%s: could not find pmic clock names
%s: old_bg_audio_users=%d old_clk_mclk_users=%d old_clk_rco_users=%d
3%s: wcd regmap is null
3%s: codec didn't set this %d!!
transport %s: get_dev_ops failed for cmpnt type %d
#
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' $x state_to_str clsh_state_fp wcd_cls_h_fsm.descriptor wcd_cls_h_fsm.descriptor.6 wcd_clsh_state_err wcd_clsh_state_ear wcd_clsh_state_hph_aux wcd_clsh_state_aux wcd_clsh_state_ear_aux wcd_clsh_state_hph_l wcd_clsh_state_hph_r wcd_clsh_state_hph_st wcd_clsh_state_hph_ear wcd_clsh_state_ear.descriptor wcd_clsh_flyback_ctrl wcd_clsh_buck_ctrl wcd_clsh_state_hph_l.descriptor wcd_clsh_state_hph_l.descriptor.36 wcd_clsh_state_hph_r.descriptor wcd_clsh_state_hph_r.descriptor.39 wcd_clsh_state_hph_st.descriptor wcd_clsh_state_aux.descriptor wcd_clsh_state_hph_aux.descriptor wcd_clsh_state_ear_aux.descriptor wcd_clsh_state_hph_ear.descriptor wcd_clsh_flyback_ctrl.descriptor wcd_clsh_buck_ctrl.descriptor $d __kstrtab_wcd_cls_h_fsm __ksymtab_wcd_cls_h_fsm __kstrtab_wcd_cls_h_init __ksymtab_wcd_cls_h_init __UNIQUE_ID_description14 __UNIQUE_ID_license15 imped_table imped_table_tavil wcd_clsh_imped_config.imped_table_ptr get_impedance_index.descriptor get_impedance_index.descriptor.13 imped_index get_impedance_index.descriptor.15 wcd_clsh_imped_config.descriptor wcd_clsh_fsm.descriptor wcd_clsh_fsm.descriptor.10 wcd_clsh_state_hph_lo wcd_clsh_state_lo wcd_clsh_state_ear_lo wcd_enable_clsh_block.descriptor wcd_clsh_set_hph_mode wcd_clsh_state_lo.descriptor is_native_44_1_active wcd_clsh_state_hph_lo.descriptor wcd_clsh_state_hph_lo.descriptor.58 wcd_clsh_state_hph_lo.descriptor.60 wcd_clsh_state_hph_lo.descriptor.62 wcd_clsh_state_ear_lo.descriptor is_native_44_1_active.descriptor __kstrtab_wcd_clsh_imped_config __ksymtab_wcd_clsh_imped_config __kstrtab_wcd_clsh_fsm __ksymtab_wcd_clsh_fsm __kstrtab_wcd_clsh_get_clsh_state __ksymtab_wcd_clsh_get_clsh_state __kstrtab_wcd_clsh_init __ksymtab_wcd_clsh_init .L21 wcd_resmgr_post_ssr_v2.descriptor wcd_resmgr_post_ssr_v2.descriptor.5 wcd_resmgr_post_ssr_v2.descriptor.7 wcd_resmgr_post_ssr_v2.descriptor.9 wcd_resmgr_enable_master_bias.descriptor wcd_resmgr_enable_clk_rco.descriptor wcd_resmgr_enable_clk_mclk.descriptor wcd_resmgr_set_sido_input_src.descriptor wcd_resmgr_set_sido_input_src.descriptor.17 wcd_resmgr_set_sido_input_src_locked.descriptor wcd_resmgr_set_sido_input_src_locked.descriptor.20 wcd_resmgr_set_sido_input_src_locked.descriptor.21 wcd_resmgr_disable_clk_rco.descriptor wcd_resmgr_disable_clk_mclk.descriptor wcd_resmgr_init.__key wcd_resmgr_init.__key.25 __kstrtab_wcd_resmgr_get_clk_type __ksymtab_wcd_resmgr_get_clk_type __kstrtab_wcd_resmgr_post_ssr_v2 __ksymtab_wcd_resmgr_post_ssr_v2 __kstrtab_wcd_resmgr_enable_master_bias __ksymtab_wcd_resmgr_enable_master_bias __kstrtab_wcd_resmgr_disable_master_bias __ksymtab_wcd_resmgr_disable_master_bias __kstrtab_wcd_resmgr_enable_clk_block __ksymtab_wcd_resmgr_enable_clk_block __kstrtab_wcd_resmgr_set_sido_input_src __ksymtab_wcd_resmgr_set_sido_input_src __kstrtab_wcd_resmgr_set_sido_input_src_locked __ksymtab_wcd_resmgr_set_sido_input_src_locked __kstrtab_wcd_resmgr_disable_clk_block __ksymtab_wcd_resmgr_disable_clk_block __kstrtab_wcd_resmgr_init __ksymtab_wcd_resmgr_init __kstrtab_wcd_resmgr_remove __ksymtab_wcd_resmgr_remove __kstrtab_wcd_resmgr_post_init __ksymtab_wcd_resmgr_post_init wcdcal_hwdep_ioctl_compat wcdcal_hwdep_ioctl wcdcal_hwdep_release wcd_cal_create_hwdep.__key wcdcal_hwdep_ioctl_shared __kstrtab_wcdcal_get_fw_cal __ksymtab_wcdcal_get_fw_cal __kstrtab_wcd_cal_create_hwdep __ksymtab_wcd_cal_create_hwdep __UNIQUE_ID_description10 __UNIQUE_ID_license11 __kstrtab_wdsp_flush_segment_list __ksymtab_wdsp_flush_segment_list __kstrtab_wdsp_get_segment_list __ksymtab_wdsp_get_segment_list wdsp_mgr_driver wdsp_mgr_probe wdsp_mgr_compare_of wdsp_load_fw_image wdsp_mgr_probe.__key wdsp_mgr_probe.__key.2 wdsp_ssr_work_fn __init_completion.__key wdsp_master_ops wdsp_mgr_remove wdsp_init_and_dload_code_sections wdsp_ssr_work_fn.descriptor wdsp_collect_ramdumps wdsp_ssr_work_fn.descriptor.38 wdsp_ssr_work_fn.descriptor.40 wdsp_ssr_work_fn.descriptor.42 wdsp_ssr_work_fn.descriptor.44 wdsp_ssr_work_fn.descriptor.45 wdsp_ssr_work_fn.descriptor.46 wdsp_ssr_work_fn.descriptor.48 wdsp_init_and_dload_code_sections.descriptor wdsp_download_segments wdsp_load_each_segment.descriptor wdsp_download_segments.descriptor wdsp_collect_ramdumps.descriptor wdsp_collect_ramdumps.descriptor.55 wdsp_mgr_bind wdsp_ops wdsp_mgr_unbind wdsp_register_cmpnt_ops wdsp_register_cmpnt_ops.descriptor wdsp_register_cmpnt_ops.descriptor.72 wdsp_get_dev_for_cmpnt wdsp_get_devops_for_cmpnt wdsp_signal_handler wdsp_signal_handler.descriptor wdsp_signal_handler.descriptor.75 wdsp_ssr_handler wdsp_debug_dump_handler.descriptor __wdsp_dbg_dump_locked wdsp_debug_dump_handler.descriptor.90 wdsp_signal_handler.descriptor.78 wdsp_vote_for_dsp wdsp_vote_for_dsp.descriptor wdsp_vote_for_dsp.descriptor.96 wdsp_enable_dsp.descriptor wdsp_enable_dsp.descriptor.107 wdsp_enable_dsp.descriptor.106 wdsp_enable_dsp.descriptor.108 wdsp_vote_for_dsp.descriptor.102 wdsp_disable_dsp.descriptor __wdsp_set_ready_locked.descriptor __wdsp_set_ready_locked.descriptor.87 wdsp_disable_dsp.descriptor.110 wdsp_disable_dsp.descriptor.111 wdsp_disable_dsp.descriptor.114 wdsp_disable_dsp.descriptor.115 wdsp_vote_for_dsp.descriptor.100 wdsp_suspend wdsp_resume wdsp_ssr_handler.descriptor wdsp_ssr_handler.descriptor.80 __wdsp_clr_ready_locked.descriptor wdsp_ssr_handler.descriptor.83 __wdsp_dbg_dump_locked.descriptor __wdsp_dbg_dump_locked.descriptor.93 wdsp_mgr_dt_match .L22 audio_ref_clk_driver audio_ref_clk_probe audio_clk_array audio_ref_clk_probe.descriptor audio_ref_clk_probe.descriptor.10 audio_ref_clk_probe.descriptor.13 audio_get_pinctrl.descriptor audio_ref_clk_remove audio_ext_clk_prepare audio_ext_clk_prepare._rs audio_ext_clk_unprepare audio_ext_clk_unprepare._rs audio_ext_clk_get_parent audio_ext_clk_get_parent.descriptor audio_ext_clk_dummy_prepare audio_ext_clk_dummy_unprepare lpass_hw_vote_prepare lpass_hw_vote_unprepare audio_ref_clk_match .compoundliteral .compoundliteral.21 .compoundliteral.23 .compoundliteral.25 .compoundliteral.27 .compoundliteral.29 .compoundliteral.31 .compoundliteral.33 .compoundliteral.35 .compoundliteral.37 audio_ext_clk_ops audio_ext_pmi_div_clk audio_ext_clk_dummy_ops .compoundliteral.20 lpass_hw_vote_ops __UNIQUE_ID_vermagic10 __UNIQUE_ID_name11 __UNIQUE_ID_intree12 ____versions __module_depends __UNIQUE_ID_alias13 __UNIQUE_ID_alias14 __UNIQUE_ID_alias15 __UNIQUE_ID_alias16 __crc_wcd_cls_h_fsm __crc_wcd_cls_h_init __stack_chk_guard dev_err __dynamic_dev_dbg __stack_chk_fail snprintf strlcat snd_soc_update_bits usleep_range __crc_wcd_clsh_imped_config __crc_wcd_clsh_fsm __crc_wcd_clsh_get_clsh_state __crc_wcd_clsh_init __dynamic_pr_debug snd_soc_read snd_soc_write wcd9xxx_slim_bulk_write __crc_wcd_resmgr_get_clk_type __crc_wcd_resmgr_post_ssr_v2 __crc_wcd_resmgr_enable_master_bias __crc_wcd_resmgr_disable_master_bias __crc_wcd_resmgr_enable_clk_block __crc_wcd_resmgr_set_sido_input_src __crc_wcd_resmgr_set_sido_input_src_locked __crc_wcd_resmgr_disable_clk_block __crc_wcd_resmgr_init __crc_wcd_resmgr_remove __crc_wcd_resmgr_post_init printk mutex_lock mutex_unlock regmap_update_bits_base regmap_read kmalloc_caches kmem_cache_alloc_trace __mutex_init __crc_wcdcal_get_fw_cal __crc_wcd_cal_create_hwdep strlen snd_hwdep_new find_next_bit set_bit cal_size_info __kmalloc cal_name_info __arch_copy_from_user memset __check_object_size init_module wcd_dsp_mgr_init audio_ref_clk_platform_init wcd_dsp_mgr_exit cleanup_module audio_ref_clk_platform_exit __crc_wdsp_flush_segment_list __crc_wdsp_get_segment_list release_firmware __list_del_entry_valid request_firmware memcmp __list_add_valid __this_module __platform_driver_register platform_driver_unregister devm_kmalloc of_property_read_string of_count_phandle_with_args of_parse_phandle_with_fixed_args devm_kfree component_match_add_release __init_waitqueue_head arch_setup_dma_ops component_master_add_with_match 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