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E'qcom,memshare!qcom,memshareqcom,client_1!qcom,memshare-peripheral R g vmodemqcom,client_2!qcom,memshare-peripheral R gmodemqcom,client_3!qcom,memshare-peripheral RP g vmodemHHqcom,sps!qcom,msm-sps-4k syscon@1f40000!sysconhwlock@1f40000!qcom,tcsr-mutex  qcom,smem@8600000 !qcom,smem IIsyscon@17c0000c!syscon ufsice@1d90000 !qcom,ice ,lufs_core_clkbus_clkiface_clkice_core_clk x   ufs_ice_noc  MINMAX!ufsufsphy_mem@1d87000p phy_mem!!$!4 lref_clk_srcref_clkref_aux_clkx% 4disabledufshc@1d84000 !qcom,ufshc@%  !H!Mufsphy!$!4!W{lcore_clkbus_aggr_clkiface_clkcore_clk_uniprocore_clk_iceref_clktx_lane0_sync_clkrx_lane0_sync_clkrx_lane1_sync_clkHx%H!h<4`<4`<4` ufshc_mem@{{{4{h{{4{h{{9{4{g{ {@ {g{{@ {@{G{{ {@ {{ {@ @{@@{t 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QQqseecom@87900000 !qcom,qseecom secapp-region$$%%%9%J%`%r%%RRsmcinvoke@87900000!qcom,smcinvoke secapp-regionSSqrng@793000 !qcom,msm-rngy0%% msm-rng-noc jjxH liface_clkTTqcedev@1de0000 !qcom,qcedev@@crypto-basecrypto-bam-base %& &&,&> qcedev-noc }}&J%J&&UUqcom_cedev_ns_cb!qcom,qcedev,context-bank ns_context0&&&&&^`&k@qcom_cedev_s_cb!qcom,qcedev,context-banksecure_context0&&&&&^&k@",qcom,msm_hdcp!qcom,msm-hdcpVVqcrypto@1de0000 !qcom,qcrypto@@crypto-basecrypto-bam-base %& &&>&,&x qcrypto-noc }}&&&&&'&J%J&&WWmem_dump!qcom,mem-dumprpmh  Erpm_sw  Epmic  Efcm  Etmc_etf  Eetf_swao  Eetr_reg  Eetf_reg  Eetfswao_reg  Emisc_data  Etz-log@146bf720 !qcom,tz-logk 0'$'8'NXXdcc_v2@10a2000 !qcom,dcc-v2  0dcc-basedcc-ram-base'aP'p'" " 0" D" X""""" " $@$@$@$@$@$@$@$@h($@   99 P99 T99 X9:  :: P:: T:: X::95P:5P # 2,2L2t22272_22282`22272_2(@(@(@(@ (@(@(@(@(@ (@$(@(( ( ( ( ( ( ( ( ( ( $( ((((( ((((( ($(((`(`(`(` (`(`(`(`(` (`$(`(  x ` ` `  `  `0 `0 `@ `@ `P `P `` `` `p `p ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` a a a a a  a  a0 a0 a@ a@ aP aP a` a` ap ap a a a a a a a a a a a a a a a a `hhh h0h@hPh`hphhѠhҠhՠh֠hhhhhhh hŠhƠh 8h  ~|   @ 7@  @ 7@ T $ @ h , "T &$ '@ 'h (, BT F$ G@ Gh H, RT V$ W@ Wh X, T $ @ h , "T &$ '@ 'h (, BT F$ G@ Gh H, RT V$ W@ Wh X, `H `T ad ap d f f g `H `T ad ap d f f gYYtsens@c222000!qcom,tsens24xx "  &0&tsens_srot_physicaltsens_tm_physical!tsens-upper-lowertsens-criticaltsens@c223000!qcom,tsens24xx "0 &P&tsens_srot_physicaltsens_tm_physical!tsens-upper-lowertsens-criticalthermal-zonesZZaoss0-usr'' 'user_space''tripsactive-config0'H'{passivecpu-0-0-usr'' 'user_space''tripsactive-config0'H'{passivecpu-0-1-usr'' 'user_space''tripsactive-config0'H'{passivecpu-0-2-usr'' 'user_space''tripsactive-config0'H'{passivecpu-0-3-usr''' 'user_space'tripsactive-config0'H'{passivecpuss-0-usr''' 'user_space'tripsactive-config0'H'{passivecpuss-1-usr''' 'user_space'tripsactive-config0'H'{passivecpu-1-0-usr''' 'user_space'tripsactive-config0'H'{passivecpu-1-1-usr''' 'user_space'tripsactive-config0'H'{passivecpu-1-2-usr'''  'user_space'tripsactive-config0'H'{passivecpu-1-3-usr'''  'user_space'tripsactive-config0'H'{passivecpu-1-4-usr'''  'user_space'tripsactive-config0'H'{passivecpu-1-5-usr'''  'user_space'tripsactive-config0'H'{passivecpu-1-6-usr'''  'user_space'tripsactive-config0'H'{passivecpu-1-7-usr''' 'user_space'tripsactive-config0'H'{passivegpuss-0-usr''' 'user_space'tripsactive-config0'H'{passiveaoss-1-usr''' 'user_space'tripsactive-config0'H'{passivecwlan-usr''' 'user_space'tripsactive-config0'H'{passivevideo-usr''' 'user_space'tripsactive-config0'H'{passiveddr-usr''' 'user_space'tripsactive-config0'H'{passiveq6-hvx-usr''' 'user_space'tripsactive-config0'H'{passivecamera-usr''' 'user_space'tripsactive-config0'H'{passivecmpss-usr''' 'user_space'tripsactive-config0'H'{passivemdm-core-usr''' 'user_space'tripsactive-config0'H'{passivenpu-usr''' 'user_space'tripsactive-config0'H'{passivemdm-vec-usr'''  'user_space'tripsactive-config0'H'{passivemdm-scl-usr'''  'user_space'tripsactive-config0'H'{passivegpuss-1-usr'' 'user_space' 'tripsactive-config0'H'{passivecpu-1-7-lowf''''low_limits_floor'(tripscpu17-trip''{passivecooling-mapscpu0_cdev( (cpu1_cdev( (cx_vdd_cdev( (mx_vdd_cdev( (ebi_vdd_cdev( (mmcx_vdd_cdev( (modem_vdd_cdev( (adsp_vdd_cdev( (cdsp_vdd_cdev( (slpi_vdd_cdev( (gpu_vdd_cdev( (gpuss-0-lowf''''low_limits_floor'(tripsgpuss0-trip''{passivecooling-mapscpu0_cdev( (cpu1_cdev( (cx_vdd_cdev( (mx_vdd_cdev( (ebi_vdd_cdev( (mmcx_vdd_cdev( (modem_vdd_cdev( (adsp_vdd_cdev( (cdsp_vdd_cdev( (slpi_vdd_cdev( (gpu_vdd_cdev( (camera-lowf''''low_limits_floor'(tripscamera-trip''{passivecooling-mapscpu0_cdev( (cpu1_cdev( (cx_vdd_cdev( (mx_vdd_cdev( (ebi_vdd_cdev( (mmcx_vdd_cdev( (modem_vdd_cdev( (adsp_vdd_cdev( (cdsp_vdd_cdev( (slpi_vdd_cdev( (gpu_vdd_cdev( (mdm-scl-lowf''' 'low_limits_floor'(tripsmdms-trip''{passivecooling-mapscpu0_cdev( (cpu1_cdev( (cx_vdd_cdev( (mx_vdd_cdev( (ebi_vdd_cdev( (mmcx_vdd_cdev( (modem_vdd_cdev( (adsp_vdd_cdev( (cdsp_vdd_cdev( (slpi_vdd_cdev( (gpu_vdd_cdev( (gpuss-max-step' 'd 'step_wise'tripsgpu-trip0'L'{passivecooling-mapsgpu_cdev( (apc-0-max-step'' 'step_wise'tripssilver-trip''{passiveapc-1-max-step'' 'step_wise'tripsgold-trip''{passivepop-mem-step' '' 'step_wise'tripspop-trip's'{passivecooling-mapspop_cdev4( (pop_cdev5( (pop_cdev6( (pop_cdev7( (lmh-dcvs-01'' 'user_space' 'tripsactive-config'L'a{passivelmh-dcvs-00'' 'user_space''tripsactive-config'L'a{passivenpu-step' '' 'step_wise'tripsnpu-trip0's'{passivecooling-mapsnpu_cdev( (cpu-0-0-step'' 'step_wise''tripscpu00-config'''{passivecooling-mapscpu00_cdev( (cpu-0-1-step'' 'step_wise''tripscpu01-config'''{passivecooling-mapscpu01_cdev( (cpu-0-2-step'' 'step_wise''tripscpu02-config'''{passivecooling-mapscpu02_cdev( (cpu-0-3-step''' 'step_wise'tripscpu03-config'''{passivecooling-mapscpu03_cdev( (cpu-1-0-step''' 'step_wise'tripscpu10-config'''{passivecooling-mapscpu10_cdev( (cpu-1-1-step''' 'step_wise'tripscpu11-config'''{passivecooling-mapscpu11_cdev( (cpu-1-2-step'''  'step_wise'tripscpu12-config'''{passivecooling-mapscpu12_cdev( (cpu-1-3-step'''  'step_wise'tripscpu13-config'''{passivecooling-mapscpu13_cdev( (cpu-1-4-step'''  'step_wise'tripscpu14-config'''{passivecooling-mapscpu14_cdev( (cpu-1-5-step'''  'step_wise'tripscpu15-config'''{passivecooling-mapscpu15_cdev( (cpu-1-6-step'''  'step_wise'tripscpu16-config'''{passivecooling-mapscpu16_cdev( (cpu-1-7-step''' 'step_wise'tripscpu17-config'''{passivecooling-mapscpu17_cdev( (pop-mem-test' '' 'step_wise'tripspop-test-trip'H'{passivecooling-mapspop_test_cdev0( (pop_test_cdev1( (pop_test_cdev2( (pop_test_cdev3( (pop_test_cdev4( ((q6-hvx-step' '' 'step_wise'tripsq6-hvx-step0's'{passiveq6-hvx-step1'('{passivecooling-mapshvx_cdev_lvl0( (hvx_cdev_lvl1( (slim@171c0000!qcom,slim-ngd@&slimbus_physicalslimbus_bam_physicalslimbus_irqslimbus_bam_irq("x(5(@[[qcom,iommu_slim_ctrl_cb!qcom,iommu-slim-ctrl-cb$&F&M&P\\msm_dai_slim!qcom,msm-dai-slim(Uslim@172400004ok!qcom,slim-ngd$ @&slimbus_physicalslimbus_bam_physical#$slimbus_irqslimbus_bam_irq(@]]qcom,iommu_slim_ctrl_cb!qcom,iommu-slim-ctrl-cb &S^^wcn3990!qcom,btfmslim_slave(U (dbtfmslim_slave_ifd(w __qcom,gpi-dma@0x800000( !qcom,gpi-dmagpi-top( (( &((4okFFqcom,gpi-dma@0xa00000( !qcom,gpi-dmagpi-top%&'()*+( (( &((4okssqcom,gpi-dma@0xc00000( !qcom,gpi-dmagpi-topLMNOPQRSTUVWX( (( &((4ok~~qcom,rmtfs_sharedmem@0!qcom,sharedmem-uio rmtfs g(qcom,msm_gsi !qcom,msm_gsiqcom,rmnet-ipa!qcom,rmnet-ipa3)))2)Pqcom,ipa@1e00000 !qcom,ipan@@ipa-basegsi-base7ipa-irqgsi-irq)e)u{))))))**ipa@ZZI Z8 'ZI8W0@@ }Z8 ZI8 88 Z$ZI$$q Z$6ZI$6$ X MINSVS2SVSNOMINALTURBO *46X*N``qcom,smp2p_map_ipa_1_out!qcom,smp2p-map-ipa-1-outipa-smp2p-outqcom,smp2p_map_ipa_1_in!qcom,smp2p-map-ipa-1-in  ipa-smp2p-inipa_smmu_ap!qcom,ipa-smmu-ap-cb & *f @ *xkk "aaipa_smmu_wlan!qcom,ipa-smmu-wlan-cb &! *xbbipa_smmu_uc!qcom,ipa-smmu-uc-cb &"*f@@ccqcom,ipa_fws!qcom,pil-tz-genericipa_fws*aop-msg-client!qcom,debugfs-qmp-clientnaopqcom,cnss-qca6390@a0000000!qcom,cnss-qca6390smmu_iova_basesmmu_iova_ipa *7}wlan_en_activewlan_en_sleep**@&J**'mhi_chan@0 LOOPBACK* +++*+8+Jmhi_chan@1 LOOPBACK* +++*+8+Jmhi_chan@4DIAG* +++*+8+Jmhi_chan@5DIAG* +++*+8+Jmhi_chan@20IPCR* +++*+8+J+Qmhi_chan@21IPCR* +++*+8+J+`+Qmhi_event@0* +o+z+++*mhi_event@1*+o+z++qcom,icnss@18800000 !qcom,icnss%membasesmmu_iova_basesmmu_iova_ipa &@+++++,, y y,+/]2ddqcom,smp2p_map_wlan_1_in8qcom,smp2p-force-fatal-errorqcom,smp2p-early-crash-indqcom,wil6210 !qcom,wil6210,C}default ,T7wil6210 dd ' 5,b,v,x%  lrf_clk3_clk,, ,),, 4disabledeemsm_tspp@0x8880000!qcom,msm_tspp p@0>MSM_TSIF0_PHYSMSM_TSIF1_PHYSMSM_TSPP_PHYSMSM_TSPP_BAM_PHYS0ywxz/TSIF_TSPP_IRQTSIF0_IRQTSIF1_IRQTSIF_BAM_IRQliface_clkref_clkxtsif RR0`Y}disabledtsif0-mode1tsif0-mode2tsif1-mode1tsif1-mode2dual-tsif-mode1dual-tsif-mode2,----&-0 & ffdemux !qcom,demuxpinctrl@03000000!qcom,sm8150-pinctrl `pinctrlspi_cfg -D-T77ufs_dev_reset_assertconfig -`ufs_reset-e-t-ufs_dev_reset_deassertconfig -`ufs_reset-e-t-storage_cdggmux-`gpio96-gpioconfig-`gpio96--tsdc2_clk_onhhconfig -`sdc2_clk--tsdc2_clk_offiiconfig -`sdc2_clk--tsdc2_clk_ds_400KHzjjconfig -`sdc2_clk--tsdc2_clk_ds_50MHzkkconfig -`sdc2_clk--tsdc2_clk_ds_100MHzllconfig -`sdc2_clk--tsdc2_clk_ds_200MHzmmconfig -`sdc2_clk--tsdc2_cmd_onnnconfig -`sdc2_cmd--tsdc2_cmd_offooconfig -`sdc2_cmd--tsdc2_cmd_ds_400KHzppconfig -`sdc2_cmd--tsdc2_cmd_ds_50MHzqqconfig -`sdc2_cmd--tsdc2_cmd_ds_100MHzrrconfig -`sdc2_cmd--tsdc2_cmd_ds_200MHzssconfig -`sdc2_cmd--tsdc2_data_onttconfig -`sdc2_data--tsdc2_data_offuuconfig -`sdc2_data--tsdc2_data_ds_400KHzvvconfig -`sdc2_data--tsdc2_data_ds_50MHzwwconfig -`sdc2_data--tsdc2_data_ds_100MHzxxconfig -`sdc2_data--tsdc2_data_ds_200MHzyyconfig -`sdc2_data--tqupv3_se12_2uart_pinszzqupv3_se12_2uart_activejjmux-`gpio85gpio86-qup12config-`gpio85gpio86-t-qupv3_se12_2uart_sleepkkmux-`gpio85gpio86-gpioconfig-`gpio85gpio86-t-equpv3_se13_4uart_pins{{qupv3_se13_default_ctsrtsrxmmmux-`gpio43gpio44gpio46-gpioconfig-`gpio43gpio44gpio46-t-equpv3_se13_default_txnnmux-`gpio45-gpioconfig-`gpio45-t-qupv3_se13_ctsrxoomux-`gpio43gpio46-qup13config-`gpio43gpio46-t-qupv3_se13_rtsppmux-`gpio44-qup13config-`gpio44-t-equpv3_se13_txqqmux-`gpio45-qup13config-`gpio45-t-pmx_ts_activets_active||mux-`gpio122gpio54-gpioconfig-`gpio122gpio54-t-pmx_ts_int_suspendts_int_suspend}}mux-`gpio122-gpioconfig-`gpio122-t-epmx_ts_reset_suspendts_reset_suspend~~mux-`gpio54-gpioconfig-`gpio54-t-epcie0pcie0_clkreq_defaultmux-`gpio36-pci_e0config-`gpio36-t-pcie0_perst_defaultmux-`gpio35-gpioconfig-`gpio35-t-epcie0_wake_defaultmux-`gpio37-gpioconfig-`gpio37-t-pcie1pcie1_clkreq_defaultmux-`gpio103-pci_e1config-`gpio103-t-pcie1_perst_defaultmux-`gpio102-gpioconfig-`gpio102-t-epcie1_wake_defaultmux-`gpio104-gpioconfig-`gpio104-t-cnss_pinscnss_wlan_en_activemux-`gpio169-gpioconfig-`gpio169-t--cnss_wlan_en_sleepmux-`gpio169-gpioconfig-`gpio169-t--epcie_eppcie_ep_clkreq_defaultmux-`gpio103-pci_e1config-`gpio103-t-pcie_ep_perst_defaultmux-`gpio102-gpioconfig-`gpio102-t-epcie_ep_wake_defaultmux-`gpio104-gpioconfig-`gpio104-t-wil6210_refclk3_en_pinmux-`gpio87-gpioconfig-`gpio87-e-tqupv3_se0_i2c_pinsqupv3_se0_i2c_activeGGmux -`gpio0gpio1-qup0config -`gpio0gpio1-t-qupv3_se0_i2c_sleepHHmux -`gpio0gpio1-gpioconfig -`gpio0gpio1-t-qupv3_se0_spi_pinsqupv3_se0_spi_activeYYmux-`gpio0gpio1gpio2gpio3-qup0config-`gpio0gpio1gpio2gpio3-t-qupv3_se0_spi_sleepZZmux-`gpio0gpio1gpio2gpio3-gpioconfig-`gpio0gpio1gpio2gpio3-t-qupv3_se1_i2c_pinsqupv3_se1_i2c_activeJJmux-`gpio114gpio115-qup1config-`gpio114gpio115-t-qupv3_se1_i2c_sleepKKmux-`gpio114gpio115-gpioconfig-`gpio114gpio115-t-qupv3_se1_spi_pinsqupv3_se1_spi_active[[mux -`gpio114gpio115gpio116gpio117-qup1config -`gpio114gpio115gpio116gpio117-t-qupv3_se1_spi_sleep\\mux -`gpio114gpio115gpio116gpio117-gpioconfig -`gpio114gpio115gpio116gpio117-t-qupv3_se2_i2c_pinsqupv3_se2_i2c_activeLLmux-`gpio126gpio127-qup2config-`gpio126gpio127-t-qupv3_se2_i2c_sleepMMmux-`gpio126gpio127-gpioconfig-`gpio126gpio127-t-qupv3_se2_spi_pinsqupv3_se2_spi_active]]mux -`gpio126gpio127gpio128gpio129-qup2config -`gpio126gpio127gpio128gpio129-t-qupv3_se2_spi_sleep^^mux -`gpio126gpio127gpio128gpio129-gpioconfig -`gpio126gpio127gpio128gpio129-t-qupv3_se3_i2c_pinsqupv3_se3_i2c_activeNNmux-`gpio144gpio145-qup3config-`gpio144gpio145-t-qupv3_se3_i2c_sleepOOmux-`gpio144gpio145-gpioconfig-`gpio144gpio145-t-qupv3_se3_spi_pinsqupv3_se3_spi_active__mux -`gpio144gpio145gpio146gpio147-qup3config -`gpio144gpio145gpio146gpio147-t-qupv3_se3_spi_sleep``mux-`gpio145gpio146gpio147-qup3config-`gpio145gpio146gpio147-t-qupv3_se3_spi_miso_sleepaamux-`gpio144-qup3config-`gpio144-t-equpv3_se4_i2c_pinsqupv3_se4_i2c_activePPmux-`gpio51gpio52-qup4config-`gpio51gpio52-t-qupv3_se4_i2c_sleepQQmux-`gpio51gpio52-gpioconfig-`gpio51gpio52-t-qupv3_se4_spi_pinsqupv3_se4_spi_activebbmux-`gpio51gpio52gpio53gpio54-qup4config-`gpio51gpio52gpio53gpio54-t-qupv3_se4_spi_sleepccmux-`gpio51gpio52gpio53gpio54-gpioconfig-`gpio51gpio52gpio53gpio54-t-qupv3_se5_i2c_pinsqupv3_se5_i2c_activeSSmux-`gpio121gpio122-qup5config-`gpio121gpio122-t-qupv3_se5_i2c_sleepTTmux-`gpio121gpio122-gpioconfig-`gpio121gpio122-t-qupv3_se5_spi_pinsqupv3_se5_spi_activeddmux -`gpio119gpio120gpio121gpio122-qup5config -`gpio119gpio120gpio121gpio122-t-qupv3_se5_spi_sleepeemux -`gpio119gpio120gpio121gpio122-gpioconfig -`gpio119gpio120gpio121gpio122-t-qupv3_se6_i2c_pinsqupv3_se6_i2c_activeUUmux -`gpio6gpio7-qup6config -`gpio6gpio7-t-qupv3_se6_i2c_sleepVVmux -`gpio6gpio7-gpioconfig -`gpio6gpio7-t-qupv3_se6_spi_pinsqupv3_se6_spi_activeffmux-`gpio4gpio5gpio6gpio7-qup6config-`gpio4gpio5gpio6gpio7-t-qupv3_se6_spi_sleepggmux-`gpio4gpio5gpio6gpio7-gpioconfig-`gpio4gpio5gpio6gpio7-t-qupv3_se7_i2c_pinsqupv3_se7_i2c_activeWWmux-`gpio98gpio99-qup7config-`gpio98gpio99-t-qupv3_se7_i2c_sleepXXmux-`gpio98gpio99-gpioconfig-`gpio98gpio99-t-qupv3_se7_spi_pinsqupv3_se7_spi_activehhmux-`gpio98gpio99gpio100gpio101-qup7config-`gpio98gpio99gpio100gpio101-t-qupv3_se7_spi_sleepiimux-`gpio98gpio99gpio100gpio101-gpioconfig-`gpio98gpio99gpio100gpio101-t-qupv3_se8_i2c_pinsqupv3_se8_i2c_activettmux-`gpio88gpio89-qup8config-`gpio88gpio89-t-qupv3_se8_i2c_sleepuumux-`gpio88gpio89-gpioconfig-`gpio88gpio89-t-qupv3_se8_spi_pinsqupv3_se8_spi_activemux-`gpio88gpio89gpio90gpio91-qup8config-`gpio88gpio89gpio90gpio91-t-qupv3_se8_spi_sleepmux-`gpio88gpio89gpio90gpio91-gpioconfig-`gpio88gpio89gpio90gpio91-t-qupv3_se9_i2c_pinsqupv3_se9_i2c_activevvmux-`gpio39gpio40-qup9config-`gpio39gpio40-t-qupv3_se9_i2c_sleepwwmux-`gpio39gpio40-gpioconfig-`gpio39gpio40-t-nfcnfc_int_activemux-`gpio47-gpioconfig-`gpio47-t-nfc_int_suspendmux-`gpio47-gpioconfig-`gpio47-t-nfc_enable_activemux-`gpio41gpio42gpio48-gpioconfig-`gpio41gpio42gpio48-t-nfc_enable_suspendmux-`gpio41gpio42gpio48-gpioconfig-`gpio41gpio42gpio48-t-nfc_clk_req_activemux-`gpio113-gpioconfig-`gpio113-t-nfc_clk_req_suspendmux-`gpio113-gpioconfig-`gpio113-t-qupv3_se9_spi_pinsqupv3_se9_spi_activemux-`gpio39gpio40gpio41gpio42-qup9config-`gpio39gpio40gpio41gpio42-t-qupv3_se9_spi_sleepmux-`gpio39gpio40gpio41gpio42-gpioconfig-`gpio39gpio40gpio41gpio42-t-qupv3_se10_i2c_pinsqupv3_se10_i2c_activexxmux -`gpio9gpio10-qup10config -`gpio9gpio10-t-qupv3_se10_i2c_sleepyymux -`gpio9gpio10-gpioconfig -`gpio9gpio10-t-qupv3_se10_spi_pinsqupv3_se10_spi_activemux-`gpio9gpio10gpio11gpio12-qup10config-`gpio9gpio10gpio11gpio12-t-qupv3_se10_spi_sleepmux-`gpio9gpio10gpio11gpio12-gpioconfig-`gpio9gpio10gpio11gpio12-t-qupv3_se11_i2c_pinsqupv3_se11_i2c_activezzmux-`gpio94gpio95-qup11config-`gpio94gpio95-t-qupv3_se11_i2c_sleep{{mux-`gpio94gpio95-gpioconfig-`gpio94gpio95-t-qupv3_se11_spi_pinsqupv3_se11_spi_activemux-`gpio92gpio93gpio94gpio95-qup11config-`gpio92gpio93gpio94gpio95-t-qupv3_se11_spi_sleepmux-`gpio92gpio93gpio94gpio95-gpioconfig-`gpio92gpio93gpio94gpio95-t-qupv3_se12_i2c_pinsqupv3_se12_i2c_active||mux-`gpio83gpio84-qup12config-`gpio83gpio84-t-qupv3_se12_i2c_sleep}}mux-`gpio83gpio84-gpioconfig-`gpio83gpio84-t-qupv3_se12_spi_pinsqupv3_se12_spi_activemux-`gpio83gpio84gpio85gpio86-qup12config-`gpio83gpio84gpio85gpio86-t-qupv3_se12_spi_sleepmux-`gpio83gpio84gpio85gpio86-gpioconfig-`gpio83gpio84gpio85gpio86-t-qupv3_se13_i2c_pinsqupv3_se13_i2c_activemux-`gpio43gpio44-qup13config-`gpio43gpio44-t-qupv3_se13_i2c_sleepmux-`gpio43gpio44-gpioconfig-`gpio43gpio44-t-qupv3_se13_spi_pinsqupv3_se13_spi_activemux-`gpio43gpio44gpio45gpio46-qup13config-`gpio43gpio44gpio45gpio46-t-qupv3_se13_spi_sleepmux-`gpio43gpio44gpio45gpio46-gpioconfig-`gpio43gpio44gpio45gpio46-t-qupv3_se14_i2c_pinsqupv3_se14_i2c_activemux-`gpio47gpio48-qup14config-`gpio47gpio48-t-qupv3_se14_i2c_sleepmux-`gpio47gpio48-gpioconfig-`gpio47gpio48-t-qupv3_se14_spi_pinsqupv3_se14_spi_activemux-`gpio47gpio48gpio49gpio50-qup14config-`gpio47gpio48gpio49gpio50-t-qupv3_se14_spi_sleepmux-`gpio47gpio48gpio49gpio50-gpioconfig-`gpio47gpio48gpio49gpio50-t-qupv3_se15_i2c_pinsqupv3_se15_i2c_activemux-`gpio27gpio28-qup15config-`gpio27gpio28-t-qupv3_se15_i2c_sleepmux-`gpio27gpio28-gpioconfig-`gpio27gpio28-t-qupv3_se15_spi_pinsqupv3_se15_spi_activemux-`gpio27gpio28gpio29gpio30-qup15config-`gpio27gpio28gpio29gpio30-t-qupv3_se15_spi_sleepmux-`gpio27gpio28gpio29gpio30-gpioconfig-`gpio27gpio28gpio29gpio30-t-qupv3_se16_i2c_pinsqupv3_se16_i2c_activemux-`gpio86gpio85-qup16config-`gpio86gpio85-t-qupv3_se16_i2c_sleepmux-`gpio86gpio85-gpioconfig-`gpio86gpio85-t-qupv3_se16_spi_pinsqupv3_se16_spi_activemux-`gpio83gpio84gpio85gpio86-qup16config-`gpio83gpio84gpio85gpio86-t-qupv3_se16_spi_sleepmux-`gpio83gpio84gpio85gpio86-gpioconfig-`gpio83gpio84gpio85gpio86-t-qupv3_se17_i2c_pinsqupv3_se17_i2c_activemux-`gpio55gpio56-qup17config-`gpio55gpio56-t-qupv3_se17_i2c_sleepmux-`gpio55gpio56-gpioconfig-`gpio55gpio56-t-qupv3_se17_spi_pinsqupv3_se17_spi_activemux-`gpio55gpio56gpio57gpio58-qup17config-`gpio55gpio56gpio57gpio58-t-qupv3_se17_spi_sleepmux-`gpio55gpio56gpio57gpio58-gpioconfig-`gpio55gpio56gpio57gpio58-t-qupv3_se18_i2c_pinsqupv3_se18_i2c_activemux-`gpio23gpio24-qup18config-`gpio23gpio24-t-qupv3_se18_i2c_sleepmux-`gpio23gpio24-gpioconfig-`gpio23gpio24-t-qupv3_se18_spi_pinsqupv3_se18_spi_activemux-`gpio23gpio24gpio25gpio26-qup18config-`gpio23gpio24gpio25gpio26-t-qupv3_se18_spi_sleepmux-`gpio23gpio24gpio25gpio26-gpioconfig-`gpio23gpio24gpio25gpio26-t-qupv3_se19_i2c_pinsqupv3_se19_i2c_activemux-`gpio57gpio58-qup19config-`gpio57gpio58-t-qupv3_se19_i2c_sleepmux-`gpio57gpio58-gpioconfig-`gpio57gpio58-t-qupv3_se19_spi_pinsqupv3_se19_spi_activemux-`gpio55gpio56gpio57gpio58-qup19config-`gpio55gpio56gpio57gpio58-t-qupv3_se19_spi_sleepmux-`gpio55gpio56gpio57gpio58-gpioconfig-`gpio55gpio56gpio57gpio58-t-aqt_intraqt_intr_defaultmux-`gpio125-gpioconfig-`gpio125-t-e-wcd9xxx_intrwcd_intr_defaultmux-`gpio123-gpioconfig-`gpio123-t-e-cdc_reset_ctrlcdc_reset_sleepmux-`gpio143-gpioconfig-`gpio143-t--cdc_reset_activemux-`gpio143-gpioconfig-`gpio143-t-e-sec_aux_pcmsec_aux_pcm_sleepmux-`gpio126gpio127-gpioconfig-`gpio126gpio127-t-e-sec_aux_pcm_activemux-`gpio126gpio127 -sec_mi2sconfig-`gpio126gpio127-t-sec_aux_pcm_dinsec_aux_pcm_din_sleepmux-`gpio128-gpioconfig-`gpio128-t-e-sec_aux_pcm_din_activemux-`gpio128 -sec_mi2sconfig-`gpio128-t-sec_aux_pcm_doutsec_aux_pcm_dout_sleepmux-`gpio129-gpioconfig-`gpio129-t-e-sec_aux_pcm_dout_activemux-`gpio129 -sec_mi2sconfig-`gpio129-t-tert_aux_pcmtert_aux_pcm_sleepmux-`gpio133gpio134-gpioconfig-`gpio133gpio134-t-e-tert_aux_pcm_activemux-`gpio133gpio134 -ter_mi2sconfig-`gpio133gpio134-t--tert_aux_pcm_dintert_aux_pcm_din_sleepmux-`gpio135-gpioconfig-`gpio135-t-e-tert_aux_pcm_din_activemux-`gpio135 -ter_mi2sconfig-`gpio135-t-tert_aux_pcm_douttert_aux_pcm_dout_sleepmux-`gpio131-gpioconfig-`gpio131-t-e-tert_aux_pcm_dout_activemux-`gpio131 -ter_mi2sconfig-`gpio131-t-quat_aux_pcmquat_aux_pcm_sleepmux-`gpio137gpio138-gpioconfig-`gpio137gpio138-t-e-quat_aux_pcm_activemux-`gpio137gpio138 -qua_mi2sconfig-`gpio137gpio138-t--quat_aux_pcm_dinquat_aux_pcm_din_sleepmux-`gpio139-gpioconfig-`gpio139-t-e-quat_aux_pcm_din_activemux-`gpio139 -qua_mi2sconfig-`gpio139-t-quat_aux_pcm_doutquat_aux_pcm_dout_sleepmux-`gpio140-gpioconfig-`gpio140-t-e-quat_aux_pcm_dout_activemux-`gpio140 -qua_mi2sconfig-`gpio140-t-pri_aux_pcm_clkpri_aux_pcm_clk_sleepmux-`gpio144-gpioconfig-`gpio144-t-e-pri_aux_pcm_clk_activemux-`gpio144 -pri_mi2sconfig-`gpio144-t--pri_aux_pcm_syncpri_aux_pcm_sync_sleepmux-`gpio145-gpioconfig-`gpio145-t-e-pri_aux_pcm_sync_activemux-`gpio145 -pri_mi2s_wsconfig-`gpio145-t--pri_aux_pcm_dinpri_aux_pcm_din_sleepmux-`gpio146-gpioconfig-`gpio146-t-e-pri_aux_pcm_din_activemux-`gpio146 -pri_mi2sconfig-`gpio146-t-pri_aux_pcm_doutpri_aux_pcm_dout_sleepmux-`gpio147-gpioconfig-`gpio147-t-e-pri_aux_pcm_dout_activemux-`gpio147 -pri_mi2sconfig-`gpio147-t-quin_aux_pcmquin_aux_pcm_sleepmux-`gpio149gpio151-gpioconfig-`gpio149gpio151-t-e-quin_aux_pcm_activemux-`gpio149gpio151 -spkr_i2sconfig-`gpio149gpio151-t--quin_aux_pcm_dinquin_aux_pcm_din_sleepmux-`gpio150-gpioconfig-`gpio150-t-e-quin_aux_pcm_din_activemux-`gpio150 -spkr_i2sconfig-`gpio150-t-quin_aux_pcm_doutquin_aux_pcm_dout_sleepmux-`gpio152-gpioconfig-`gpio152-t-e-quin_aux_pcm_dout_activemux-`gpio152 -spkr_i2sconfig-`gpio152-t-sec_tdmsec_tdm_sleepmux-`gpio126gpio127-gpioconfig-`gpio126gpio127-t-e-sec_tdm_activemux-`gpio126gpio127 -sec_mi2sconfig-`gpio126gpio127-t-sec_tdm_dinsec_tdm_din_sleepmux-`gpio128-gpioconfig-`gpio128-t-e-sec_tdm_din_activemux-`gpio128 -sec_mi2sconfig-`gpio128-t-sec_tdm_doutsec_tdm_dout_sleepmux-`gpio129-gpioconfig-`gpio129-t-e-sec_tdm_dout_activemux-`gpio129 -sec_mi2sconfig-`gpio129-t-tert_tdmtert_tdm_sleepmux-`gpio133gpio134-gpioconfig-`gpio133gpio134-t-e-tert_tdm_activemux-`gpio133gpio134 -ter_mi2sconfig-`gpio133gpio134-t--tert_tdm_dintert_tdm_din_sleepmux-`gpio135-gpioconfig-`gpio135-t-e-tert_tdm_din_activemux-`gpio135 -ter_mi2sconfig-`gpio135-t-tert_tdm_douttert_tdm_dout_sleepmux-`gpio131-gpioconfig-`gpio131-t-e-tert_tdm_dout_activemux-`gpio131 -ter_mi2sconfig-`gpio131-t-quat_tdmquat_tdm_sleepmux-`gpio137gpio138-gpioconfig-`gpio137gpio138-t-e-quat_tdm_activemux-`gpio137gpio138 -qua_mi2sconfig-`gpio137gpio138-t--quat_tdm_dinquat_tdm_din_sleepmux-`gpio139-gpioconfig-`gpio139-t-e-quat_tdm_din_activemux-`gpio139 -qua_mi2sconfig-`gpio139-t-quat_tdm_doutquat_tdm_dout_sleepmux-`gpio140-gpioconfig-`gpio140-t-e-quat_tdm_dout_activemux-`gpio140 -qua_mi2sconfig-`gpio140-t-pri_tdm_clkpri_tdm_clk_sleepmux-`gpio144-gpioconfig-`gpio144-t-e-pri_tdm_clk_activemux-`gpio144 -pri_mi2sconfig-`gpio144-t--pri_tdm_syncpri_tdm_sync_sleepmux-`gpio145-gpioconfig-`gpio145-t-e-pri_tdm_sync_activemux-`gpio145 -pri_mi2s_wsconfig-`gpio145-t--pri_tdm_dinpri_tdm_din_sleepmux-`gpio146-gpioconfig-`gpio146-t-e-pri_tdm_din_activemux-`gpio146 -pri_mi2sconfig-`gpio146-t-pri_tdm_doutpri_tdm_dout_sleepmux-`gpio147-gpioconfig-`gpio147-t-e-pri_tdm_dout_activemux-`gpio147 -pri_mi2sconfig-`gpio147-t-quin_tdmquin_tdm_sleepmux-`gpio149gpio151-gpioconfig-`gpio149gpio151-t-e-quin_tdm_activemux-`gpio149gpio151 -spkr_i2sconfig-`gpio149gpio151-t--quin_tdm_dinquin_tdm_din_sleepmux-`gpio150-gpioconfig-`gpio150-t-e-quin_tdm_din_activemux-`gpio150 -spkr_i2sconfig-`gpio150-t-quin_tdm_doutquin_tdm_dout_sleepmux-`gpio152-gpioconfig-`gpio152-t-e-quin_tdm_dout_activemux-`gpio152 -spkr_i2sconfig-`gpio152-t-sec_mi2s_mclksec_mi2s_mclk_sleepmux-`gpio130-gpioconfig-`gpio130-t-e-sec_mi2s_mclk_activemux-`gpio130 -sec_mi2sconfig-`gpio130-t-sec_mi2ssec_mi2s_sleepmux-`gpio126gpio127-gpioconfig-`gpio126gpio127-t--sec_mi2s_activemux-`gpio126gpio127 -sec_mi2sconfig-`gpio126gpio127-t-sec_mi2s_sd0sec_mi2s_sd0_sleepmux-`gpio128-gpioconfig-`gpio128-t-e-sec_mi2s_sd0_activemux-`gpio128 -sec_mi2sconfig-`gpio128-t-sec_mi2s_sd1sec_mi2s_sd1_sleepmux-`gpio129-gpioconfig-`gpio129-t-e-sec_mi2s_sd1_activemux-`gpio129 -sec_mi2sconfig-`gpio129-t-tert_mi2s_mclktert_mi2s_mclk_sleepmux-`gpio132-gpioconfig-`gpio132-t-e-tert_mi2s_mclk_activemux-`gpio132 -ter_mi2sconfig-`gpio132-t-tert_mi2stert_mi2s_sleepmux-`gpio133gpio134-gpioconfig-`gpio133gpio134-t-e-tert_mi2s_activemux-`gpio133gpio134 -ter_mi2sconfig-`gpio133gpio134-t--tert_mi2s_sd0tert_mi2s_sd0_sleepmux-`gpio135-gpioconfig-`gpio135-t-e-tert_mi2s_sd0_activemux-`gpio135 -ter_mi2sconfig-`gpio135-t-tert_mi2s_sd1tert_mi2s_sd1_sleepmux-`gpio131-gpioconfig-`gpio131-t-e-tert_mi2s_sd1_activemux-`gpio131 -ter_mi2sconfig-`gpio131-t-quat_mi2s_mclkquat_mi2s_mclk_sleepmux-`gpio136-gpioconfig-`gpio136-t-e-quat_mi2s_mclk_activemux-`gpio136 -qua_mi2sconfig-`gpio136-t-quat_mi2squat_mi2s_sleepmux-`gpio137gpio138-gpioconfig-`gpio137gpio138-t-e-quat_mi2s_activemux-`gpio137gpio138 -qua_mi2sconfig-`gpio137gpio138-t--quat_mi2s_sd0quat_mi2s_sd0_sleepmux-`gpio139-gpioconfig-`gpio139-t-e-quat_mi2s_sd0_active  mux-`gpio139 -qua_mi2sconfig-`gpio139-t-quat_mi2s_sd1quat_mi2s_sd1_sleep  mux-`gpio140-gpioconfig-`gpio140-t-e-quat_mi2s_sd1_active  mux-`gpio140 -qua_mi2sconfig-`gpio140-t-quat_mi2s_sd2quat_mi2s_sd2_sleep  mux-`gpio141-gpioconfig-`gpio141-t-e-quat_mi2s_sd2_active  mux-`gpio141 -qua_mi2sconfig-`gpio141-t-quat_mi2s_sd3quat_mi2s_sd3_sleepmux-`gpio142-gpioconfig-`gpio142-t-e-quat_mi2s_sd3_activemux-`gpio142 -qua_mi2sconfig-`gpio142-t-pri_mi2s_mclkpri_mi2s_mclk_sleepmux-`gpio143-gpioconfig-`gpio143-t-e-pri_mi2s_mclk_activemux-`gpio143 -pri_mi2sconfig-`gpio143-t--pri_mi2s_sckpri_mi2s_sck_sleepmux-`gpio144-gpioconfig-`gpio144-t-e-pri_mi2s_sck_activemux-`gpio144 -pri_mi2sconfig-`gpio144-t--pri_mi2s_wspri_mi2s_ws_sleepmux-`gpio145-gpioconfig-`gpio145-t-e-pri_mi2s_ws_activemux-`gpio145 -pri_mi2s_wsconfig-`gpio145-t--pri_mi2s_sd0pri_mi2s_sd0_sleepmux-`gpio146-gpioconfig-`gpio146-t-e-pri_mi2s_sd0_activemux-`gpio146 -pri_mi2sconfig-`gpio146-t-pri_mi2s_sd1pri_mi2s_sd1_sleepmux-`gpio147-gpioconfig-`gpio147-t-e-pri_mi2s_sd1_activemux-`gpio147 -pri_mi2sconfig-`gpio147-t-quin_mi2s_mclkquin_mi2s_mclk_sleepmux-`gpio148-gpioconfig-`gpio148-t-equin_mi2s_mclk_activemux-`gpio148 -spkr_i2sconfig-`gpio148-t-quin_mi2squin_mi2s_sleepmux-`gpio149gpio151-gpioconfig-`gpio149gpio151-t-e-quin_mi2s_activemux-`gpio149gpio151 -spkr_i2sconfig-`gpio149gpio151-t--quin_mi2s_sd0quin_mi2s_sd0_sleepmux-`gpio150-gpioconfig-`gpio150-t-e-quin_mi2s_sd0_activemux-`gpio150 -spkr_i2sconfig-`gpio150-t-quin_mi2s_sd1quin_mi2s_sd1_sleep  mux-`gpio152-gpioconfig-`gpio152-t-e-quin_mi2s_sd1_active!!mux-`gpio152 -spkr_i2sconfig-`gpio152-t-pmx_sde""sde_dsi_active##mux -`gpio6gpio7-gpioconfig -`gpio6gpio7-t-sde_dsi_suspend$$mux -`gpio6gpio7-gpioconfig -`gpio6gpio7-t-esde_dsi1_active%%mux-`gpio130-gpioconfig-`gpio130-t-sde_dsi1_suspend&&mux-`gpio130-gpioconfig-`gpio130-t-epmx_sde_tesde_te_active''mux-`gpio8 -mdp_vsyncconfig-`gpio8-t-esde_te_suspend((mux-`gpio8 -mdp_vsyncconfig-`gpio8-t-esde_te1_active))mux-`gpio9 -mdp_vsyncconfig-`gpio9-t-esde_te1_suspend**mux-`gpio9 -mdp_vsyncconfig-`gpio9-t-esde_dp_usbplug_cc_active++mux-`gpio38-gpioconfig-`gpio38--tsde_dp_usbplug_cc_suspend,,mux-`gpio38-gpioconfig-`gpio38-e-tap2mdmap2mdm_active--mux-`gpio135gpio141-gpioconfig-`gpio135gpio141-t-ap2mdm_sleep..mux-`gpio135gpio141-gpioconfig-`gpio135gpio141-t-mdm2apmdm2ap_active//mux-`gpio142gpio53-gpioconfig-`gpio142gpio53-t-mdm2ap_sleep00mux-`gpio142gpio53-gpioconfig-`gpio142gpio53-t-fsa_usbc_ana_en_n@100fsa_usbc_ana_enRRmux-`gpio100-gpioconfig-`gpio100-t--cam_sensor_mclk0_active11mux-`gpio13 -cam_mclkconfig-`gpio13--tcam_sensor_mclk0_suspend22mux-`gpio13 -cam_mclkconfig-`gpio13-e-tcam_sensor_mclk1_active33mux-`gpio14 -cam_mclkconfig-`gpio14--tcam_sensor_mclk1_suspend44mux-`gpio14 -cam_mclkconfig-`gpio14-e-tcam_sensor_mclk2_active55mux-`gpio15 -cam_mclkconfig-`gpio15--tcam_sensor_mclk2_suspend66mux-`gpio15 -cam_mclkconfig-`gpio15-e-tcam_sensor_mclk3_active77mux-`gpio16 -cam_mclkconfig-`gpio16--tcam_sensor_mclk3_suspend88mux-`gpio16 -cam_mclkconfig-`gpio16-e-tcam_sensor_eldo2_default99mux-`gpio11-gpioconfig-`gpio11--tcamera_vaf_en_default::mux-`gpio29-gpioconfig-`gpio29--tcamera_vana_en_default;;mux-`gpio11-gpioconfig-`gpio11--tcam_sensor_active_rear<<mux-`gpio28-gpioconfig-`gpio28--tcam_sensor_suspend_rear==mux-`gpio28-gpioconfig-`gpio28-e-t-cam_sensor_active_rear_aux>>mux-`gpio30-gpioconfig-`gpio30--tcam_sensor_suspend_rear_aux??mux-`gpio30-gpioconfig-`gpio30-e-t-cam_sensor_active_front@@mux-`gpio12-gpioconfig-`gpio12--tcam_sensor_suspend_frontAAmux-`gpio12-gpioconfig-`gpio12-e-t-cam_sensor_active_irisBBmux-`gpio23gpio26-gpioconfig-`gpio23gpio26--tcam_sensor_suspend_irisCCmux-`gpio23gpio26-gpioconfig-`gpio23gpio26-e-t-cam_sensor_active_triple_rearDDmux-`gpio30gpio157gpio158-gpioconfig-`gpio30gpio157gpio158--tcam_sensor_suspend_triple_rearEEmux-`gpio30gpio157gpio158-gpioconfig-`gpio30gpio157gpio158-e-t-cam_sensor_active_triple_rear_auxFFmux-`gpio23gpio159gpio160-gpioconfig-`gpio23gpio159gpio160--tcam_sensor_suspend_triple_rear_auxGGmux-`gpio23gpio159gpio160-gpioconfig-`gpio23gpio159gpio160-e-t-cam_sensor_active_triple_rear_aux2HHmux-`gpio28gpio24gpio25-gpioconfig-`gpio28gpio24gpio25--tcam_sensor_suspend_triple_rear_aux2IImux-`gpio28gpio24gpio25-gpioconfig-`gpio28gpio24gpio25-e-t-cci0_active33mux-`gpio17gpio18-cci_i2cconfig-`gpio17gpio18--tcci0_suspend55mux-`gpio17gpio18-cci_i2cconfig-`gpio17gpio18-e-tcci1_active44mux-`gpio19gpio20-cci_i2cconfig-`gpio19gpio20--tcci1_suspend66mux-`gpio19gpio20-cci_i2cconfig-`gpio19gpio20-e-tcci2_active88mux-`gpio31gpio32-cci_i2cconfig-`gpio31gpio32--tcci2_suspend::mux-`gpio31gpio32-cci_i2cconfig-`gpio31gpio32-e-tcci3_active99mux-`gpio33gpio34-cci_i2cconfig-`gpio33gpio34--tcci3_suspend;;mux-`gpio33gpio34-cci_i2cconfig-`gpio33gpio34-e-ttsif0_signals_activetsif1_clk-`gpio88 -tsif1_clktsif1_en-`gpio89 -tsif1_entsif1_data-`gpio90 -tsif1_datasignals_cfg-`gpio88gpio89gpio90--etsif0_sync_activetsif1_sync-`gpio91 -tsif1_sync--etsif1_signals_activetsif2_clk-`gpio92 -tsif2_clktsif2_en-`gpio93 -tsif2_entsif2_data-`gpio94 -tsif2_datasignals_cfg-`gpio92gpio93gpio94--etsif1_sync_activetsif2_sync-`gpio95 -tsif2_sync--etrigout_a!!mux-`gpio49 -qdss_cticonfig-`gpio49-t-usb2_id_det_defaultJJconfig-`gpio101-gpio--emacemac_mdcKKmux-`gpio7 -rgmii_mdcconfig-`gpio7-emac_mdioLLmux-`gpio59 -rgmii_mdioconfig-`gpio59-emac_rgmii_txd0MMmux-`gpio122 -rgmii_txd0config-`gpio122--temac_rgmii_txd1NNmux-`gpio4 -rgmii_txd1config-`gpio4--temac_rgmii_txd2OOmux-`gpio5 -rgmii_txd2config-`gpio5--temac_rgmii_txd3PPmux-`gpio6 -rgmii_txd3config-`gpio6--temac_rgmii_txcQQmux-`gpio114 -rgmii_txcconfig-`gpio114--temac_rgmii_tx_ctlRRmux-`gpio121 -rgmii_txconfig-`gpio121--temac_rgmii_rxd0SSmux-`gpio117 -rgmii_rxd0config-`gpio117--temac_rgmii_rxd1TTmux-`gpio118 -rgmii_rxd1config-`gpio118--temac_rgmii_rxd2UUmux-`gpio119 -rgmii_rxd2config-`gpio119--temac_rgmii_rxd3VVmux-`gpio120 -rgmii_rxd3config-`gpio120--temac_rgmii_rxcWWmux-`gpio115 -rgmii_rxcconfig-`gpio115--temac_rgmii_rx_ctlXXmux-`gpio116 -rgmii_rxconfig-`gpio116--temac_phy_intrYYmux-`gpio124 -emac_phyconfig-`gpio124--temac_phy_reset_stateZZmux-`gpio79-gpioconfig-`gpio79--temac_pin_pps_0[[mux-`gpio81 -emac_ppsconfig-`gpio81-t-bt_en_active\\mux-`gpio172-gpioconfig-`gpio172-t-econn_power_1p8_active]]mux-`gpio173-gpioconfig-`gpio173-t-conn_power_pa_active^^mux-`gpio174-gpioconfig-`gpio174-t-usb2phy_ac_en1_default__mux-`gpio113 -usb2phy_acconfig-`gpio113-t-usb2phy_ac_en2_default``mux-`gpio123 -usb2phy_acconfig-`gpio123-t-audio_ioexp_reset_activeaamux-`gpio166-gpioconfig-`gpio166-t--slpi_pinctrl@02B40000!qcom,slpi-pinctrl- 4disabledbbqupv3_se20_i2c_pinsccqupv3_se20_i2c_activemux -`gpio0gpio1-func1config -`gpio0gpio1-t-qupv3_se20_i2c_sleepmux -`gpio0gpio1-gpioconfig -`gpio0gpio1-t-qupv3_se21_i2c_pinsddqupv3_se21_i2c_activemux -`gpi2gpio3-func1config -`gpio2gpio3-t-qupv3_se21_i2c_sleepmux -`gpio2gpio3-gpioconfig -`gpio2gpio3-t-qupv3_se22_i2c_pinseequpv3_se22_i2c_activemux -`gpio6gpio7-func1config -`gpio6gpio7-t-qupv3_se22_i2c_sleepmux -`gpio6gpio7-gpioconfig -`gpio6gpio7-t-qupv3_se23_i2c_pinsffqupv3_se23_i2c_activemux -`gpio8gpio9-func3config -`gpio8gpio9-t-qupv3_se23_i2c_sleepmux -`gpio8gpio9-gpioconfig -`gpio8gpio9-t-qupv3_se21_spi_pinsggqupv3_se21_spi_activemux-`gpio2gpio3gpio4gpio5-func1config-`gpio2gpio3gpio4gpio5-t-qupv3_se21_spi_sleepmux-`gpio2gpio3gpio4gpio5-gpioconfig-`gpio2gpio3gpio4gpio5-t-qupv3_se22_spi_pinshhqupv3_se22_spi_activemux-`gpio6gpio7gpio8gpio9-func1config-`gpio6gpio7gpio8gpio9-t-qupv3_se22_spi_sleepmux-`gpio6gpio7gpio8gpio9-gpioconfig-`gpio6gpio7gpio8gpio9-t-regulator-pm8150-s4!qcom,stub-regulator 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%pm8150l_l10.<--.2.]-.rpmh-regulator-ldoc11!qcom,rpmh-vrm-regulatornU.)ldoc11 .pmic5-ldo..regulator-pm8150l-l11 %pm8150l_l11.<--.2.]-.rpmh-regulator-bobc1!qcom,rpmh-vrm-regulatornU.)bobc1 .pmic5-bob . .B@/regulator-pm8150l-bob %pm8150l_bob.<--.= .]2.regulator-pm8150l-bob-ao%pm8150l_bob_ao.<--.= .]-.rpmh-regulator-smpf2!qcom,rpmh-xob-regulatornU.)smpf2regulator-pm8009-s2 %pm8009_s2.<-+@.+@rpmh-regulator-ldof2!qcom,rpmh-xob-regulatornU.)ldof2regulator-pm8009-l2 %pm8009_l2.<-O.Orpmh-regulator-ldof5!qcom,rpmh-xob-regulatornU.)ldof5regulator-pm8009-l5 %pm8009_l5.<-*.*rpmh-regulator-ldof6!qcom,rpmh-xob-regulatornU.)ldof6regulator-pm8009-l6 %pm8009_l6.<-+@.+@refgen-regulator@88e7000!qcom,refgen-regulatorp`%refgen/qcom,ion !qcom,msm-ionqcom,ion-heap@25/SYSTEMqcom,ion-heap@22/DMAqcom,ion-heap@26/DMAqcom,ion-heap@27/DMAqcom,ion-heap@19/DMAqcom,ion-heap@13 /HYP_CMAqcom,ion-heap@10 /HYP_CMAqcom,ion-heap@9 /SYSTEM_SECUREad-hoc-bus!qcom,msm-bus-device`npPN h htbbbpaggre1_noc-baseaggre2_noc-baseconfig_noc-basedc_noc-basegladiator_noc-basemc_virt-basegem_noc-basemmss_noc-basesystem_noc-baseipa_virt-basecamnoc_virt-basecompute_noc-baseapps_rscdisp_rscnU'rsc-apps/@ apps_rsc//rsc-disp/A disp_rsc//bcm-acv/~ACV/ACV00 bcm-alc/ALC/ALC00 hhbcm-mc0/XMC0/MC000 bcm-sh0/[SH0/SH000 bcm-mm0/cMM0/MM000 bcm-mm1/dMM1/MM100   bcm-sh2/]SH2/SH200 bcm-mm2/eMM2/MM200 VVbcm-sh3/^SH3/SH300 JJbcm-mm3/fMM3/MM300 WWbcm-sh4/_SH4/SH400 MMbcm-sh5/`SH5/SH500 IIbcm-sn0/jSN0/SN000 bcm-co0/CO0/CO000 xxbcm-ce0/zCE0/CE000 bcm-sn1/kSN1/SN100 bcm-co1/CO1/CO100   bcm-ip0/{IP0/IP000 bcm-cn0/|CN0/CN000 bcm-qup0/QUP0/QUP000 bcm-sn2/lSN2/SN200 bcm-sn3/mSN3/SN300 ssbcm-sn4/nSN4/SN400 bcm-sn5/oSN5/SN500 bcm-sn8/rSN8/SN800 bcm-sn9/sSN9/SN900 ``bcm-sn11/uSN11/SN1100 ddbcm-sn12/vSN12/SN1200 ggbcm-sn14/xSN14/SN1400 vvbcm-sn15/ySN15/SN1500 eebcm-acv_display/i~ ACV_DISPLAY/ACV00 bcm-alc_display/i ALC_DISPLAY/ALC00 bcm-mc0_display/ix MC0_DISPLAY/MC000 bcm-sh0_display/iy SH0_DISPLAY/SH000 bcm-mm0_display/iz MM0_DISPLAY/MM000 bcm-mm1_display/i{ MM1_DISPLAY/MM100 oobcm-mm2_display/i| MM2_DISPLAY/MM200 bcm-mm3_display/i} MM3_DISPLAY/MM300 qqfab-aggre1_noc/fab-aggre1_noc00'aggre1_noc-base060C@0Txfab-aggre2_noc/fab-aggre2_noc00'aggre2_noc-base060C`0Txfab-camnoc_virt/ fab-camnoc_virt00'camnoc_virt-base060C0bxfab-compute_noc/ fab-compute_noc00'compute_noc-base06 0C0Tx  fab-config_noc/fab-config_noc00'config_noc-base060C0v`0Txfab-dc_noc/ fab-dc_noc0 0'dc_noc-base060C0b0TxDDfab-gem_noc/  fab-gem_noc0 0'gem_noc-base060C0TxHHfab-ipa_virt/  fab-ipa_virt00'ipa_virt-base060C0bxOOfab-mc_virt/ fab-mc_virt0 0'mc_virt-base060C0bxQQfab-mmss_noc/ fab-mmss_noc00'mmss_noc-base060C0TxSSfab-system_noc/fab-system_noc00'system_noc-base060C0TxYYfab-gem_noc_display/efab-gem_noc_display0 0'gem_noc-base060C0b0Txjjfab-mc_virt_display/efab-mc_virt_display0 0'mc_virt-base060C0bxllfab-mmss_noc_display/efab-mmss_noc_display00'mmss_noc-base060C0b0Txnnmas-qhm-a1noc-cfg/ymas-qhm-a1noc-cfg0000yymas-qhm-qup0/ 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mas-qxm-camnoc-sf-uncomp/mas-qxm-camnoc-sf-uncomp0 0000 mas-qnm-npu/ mas-qnm-npu0 000 0 0 000mas-qhm-spdm/$ mas-qhm-spdm000 00mas-qnm-snoc/'3 mas-qnm-snoc000 !"#$%&'()*+,-./0123456789:;<=>?@A00mas-xm-qdss-dap/Lmas-xm-qdss-dap000 !"#$ %&'()*+,-./0123456789:;<=>?@A0mas-qhm-cnoc-dc-noc/~mas-qhm-cnoc-dc-noc000BC0D{{mas-acm-apps/ mas-acm-apps0 00`abc 0EFG0H0I000mas-acm-gpu-tcu/mas-acm-gpu-tcu000`0FG0H0J00mas-acm-sys-tcu/mas-acm-sys-tcu0000FG0H0J00mas-qhm-gemnoc-cfg/mas-qhm-gemnoc-cfg000KL0Hmas-qnm-cmpnoc/mas-qnm-cmpnoc0 00@A 0EFG0H0M000wwmas-qnm-gpu/ mas-qnm-gpu0 00 !0FG0H00mas-qnm-mnoc-hf/mas-qnm-mnoc-hf0 000F0H00 1dmas-qnm-mnoc-sf/mas-qnm-mnoc-sf0 00@0FG0H00 1dmas-qnm-pcie/ mas-qnm-pcie0000FG0H000uumas-qnm-snoc-gc/mas-qnm-snoc-gc0000F0H000mas-qnm-snoc-sf/mas-qnm-snoc-sf0000F0H000mas-qxm-ecc/ mas-qxm-ecc0 000F0H000mas-ipa-core-master/mas-ipa-core-master000N0Omas-llcc-mc/ mas-llcc-mc000P0Qmas-qhm-mnoc-cfg/gmas-qhm-mnoc-cfg000R0S||mas-qxm-camnoc-hf0/mas-qxm-camnoc-hf00 000T0S0 000 1dmas-qxm-camnoc-hf1/mas-qxm-camnoc-hf10 000T0S0 000 1dmas-qxm-camnoc-sf/mas-qxm-camnoc-sf0 000U0S0V000 1dmas-qxm-mdp0/ mas-qxm-mdp00 000T0S0 000 1dmas-qxm-mdp1/ mas-qxm-mdp10 000T0S0 000 1dmas-qxm-rot/ mas-qxm-rot0 000U0S0W000 1dmas-qxm-venus0/?mas-qxm-venus00 000U0S0W000 1dmas-qxm-venus1/@mas-qxm-venus10 000U0S0W000 1dmas-qxm-venus-arm9/mas-qxm-venus-arm90000U0S0W000 1dmas-qhm-snoc-cfg/6mas-qhm-snoc-cfg000X0Y}}mas-qnm-aggre1-noc/'Omas-qnm-aggre1-noc000Z[\]^_0Y0`rrmas-qnm-aggre2-noc/'Pmas-qnm-aggre2-noc00$0Z[\]^abc_0Y0dttmas-qnm-gemnoc/mas-qnm-gemnoc000[\]^c_0Y0emas-qxm-pimem/mas-qxm-pimem0000f\0Y0g000mas-xm-gic/ mas-xm-gic0000f\0Y0g000mas-alc/mas-alc000Q0hmas-qnm-mnoc-hf_display/N!mas-qnm-mnoc-hf_display0 000i0jmas-qnm-mnoc-sf_display/N"mas-qnm-mnoc-sf_display0 00@0i0jmas-llcc-mc_display/N mas-llcc-mc_display000k0lmas-qxm-mdp0_display/N#mas-qxm-mdp0_display0 000m0n0omas-qxm-mdp1_display/N$mas-qxm-mdp1_display0 000m0n0omas-qxm-rot_display/N%mas-qxm-rot_display0 000p0n0qslv-qns-a1noc-snoc/'Nslv-qns-a1noc-snoc0000rslv-srvc-aggre1-noc/slv-srvc-aggre1-noc0000sslv-qns-a2noc-snoc/'Qslv-qns-a2noc-snoc0000tslv-qns-pcie-mem-noc/'Uslv-qns-pcie-mem-noc0000u0vslv-srvc-aggre2-noc/slv-srvc-aggre2-noc0000sslv-qns-camnoc-uncomp/ slv-qns-camnoc-uncomp0 00slv-qns-cdsp-mem-noc/'Vslv-qns-cdsp-mem-noc0 00 0w0x  slv-qhs-a1-noc-cfg/slv-qhs-a1-noc-cfg0000y066slv-qhs-a2-noc-cfg/slv-qhs-a2-noc-cfg0000z0  slv-qhs-ahb2phy-south/ slv-qhs-ahb2phy-south0000//slv-qhs-aop/ slv-qhs-aop0000--slv-qhs-aoss/ slv-qhs-aoss000077slv-qhs-camera-cfg/Mslv-qhs-camera-cfg0000 1% "18mmcxslv-qhs-clk-ctl/lslv-qhs-clk-ctl0000,,slv-qhs-compute-dsp/slv-qhs-compute-dsp0000slv-qhs-cpr-cx/slv-qhs-cpr-cx000044slv-qhs-cpr-mmcx/ slv-qhs-cpr-mmcx0000%%slv-qhs-cpr-mx/slv-qhs-cpr-mx0000@@slv-qhs-crypto0-cfg/qslv-qhs-crypto0-cfg0000==slv-qhs-ddrss-cfg/slv-qhs-ddrss-cfg0000{0$$slv-qhs-display-cfg/Nslv-qhs-display-cfg00001% 18mmcx""slv-qhs-emac-cfg/ slv-qhs-emac-cfg0000slv-qhs-glm/ slv-qhs-glm0000slv-qhs-gpuss-cfg/Vslv-qhs-gpuss-cfg0000((slv-qhs-imem-cfg/sslv-qhs-imem-cfg0000AAslv-qhs-ipa/ slv-qhs-ipa0000++slv-qhs-mnoc-cfg/slv-qhs-mnoc-cfg0000|0slv-qhs-npu-cfg/slv-qhs-npu-cfg0000&&slv-qhs-pcie0-cfg/slv-qhs-pcie0-cfg0000''slv-qhs-pcie1-cfg/slv-qhs-pcie1-cfg0000slv-qhs-phy-refgen-north/slv-qhs-phy-refgen-north0000slv-qhs-pimem-cfg/slv-qhs-pimem-cfg0000>>slv-qhs-prng/j slv-qhs-prng000088slv-qhs-qdss-cfg/{slv-qhs-qdss-cfg0000!!slv-qhs-qspi/ slv-qhs-qspi0000::slv-qhs-qupv3-east/slv-qhs-qupv3-east000033slv-qhs-qupv3-north/slv-qhs-qupv3-north0000..slv-qhs-qupv3-south/slv-qhs-qupv3-south0000slv-qhs-sdc2/` slv-qhs-sdc20000slv-qhs-sdc4/a slv-qhs-sdc40000slv-qhs-snoc-cfg/slv-qhs-snoc-cfg0000}0slv-qhs-spdm/y slv-qhs-spdm0000<<slv-qhs-spss-cfg/slv-qhs-spss-cfg0000slv-qhs-ssc-cfg/slv-qhs-ssc-cfg0000slv-qhs-tcsr/o slv-qhs-tcsr0000##slv-qhs-tlmm-east/slv-qhs-tlmm-east0000slv-qhs-tlmm-north/slv-qhs-tlmm-north0000??slv-qhs-tlmm-south/slv-qhs-tlmm-south0000slv-qhs-tlmm-west/slv-qhs-tlmm-west000055slv-qhs-tsif/? slv-qhs-tsif0000**slv-qhs-ufs-card-cfg/slv-qhs-ufs-card-cfg000022slv-qhs-ufs-mem-cfg/slv-qhs-ufs-mem-cfg0000slv-qhs-usb3-0/Gslv-qhs-usb3-00000;;slv-qhs-usb3-1/slv-qhs-usb3-1000000slv-qhs-venus-cfg/Tslv-qhs-venus-cfg0000 1%#18mmcx))slv-qhs-vsense-ctrl-cfg/slv-qhs-vsense-ctrl-cfg000099slv-qns-cnoc-a2noc/slv-qns-cnoc-a2noc0000~0  slv-srvc-cnoc/slv-srvc-cnoc000011slv-qhs-llcc/ slv-qhs-llcc000DCCslv-qhs-memnoc/slv-qhs-memnoc000D0BBslv-qhs-mdsp-ms-mpu-cfg/slv-qhs-mdsp-ms-mpu-cfg000HLLslv-qns-ecc/ slv-qns-ecc0 00HEEslv-qns-gem-noc-snoc/'Wslv-qns-gem-noc-snoc000H00GGslv-qns-llcc/ slv-qns-llcc000H00FFslv-srvc-gemnoc/slv-srvc-gemnoc000HKKslv-ipa-core-slave/ slv-ipa-core-slave000O0NNslv-ebi/slv-ebi000Q0PPslv-qns2-mem-noc/slv-qns2-mem-noc0 00S00VUUslv-qns-mem-noc-hf/slv-qns-mem-noc-hf0 00S00TTslv-srvc-mnoc/[slv-srvc-mnoc000SRRslv-qhs-apss/ slv-qhs-apss000Y]]slv-qns-cnoc/'4 slv-qns-cnoc000Y00s^^slv-qns-gemnoc-gc/'Xslv-qns-gemnoc-gc000Y00ffslv-qns-gemnoc-sf/'Yslv-qns-gemnoc-sf000Y00ZZslv-qxs-imem/I slv-qxs-imem000Y0\\slv-qxs-pimem/slv-qxs-pimem000Y0[[slv-srvc-snoc/Kslv-srvc-snoc000YXXslv-xs-pcie-0/slv-xs-pcie-0000Y0aaslv-xs-pcie-1/slv-xs-pcie-1000Y0bbslv-xs-qdss-stm/Lslv-xs-qdss-stm000Y0__slv-xs-sys-tcu-cfg/slv-xs-sys-tcu-cfg000Yccslv-qns-llcc_display/P!slv-qns-llcc_display000j00iislv-ebi_display/P slv-ebi_display000l0kkslv-qns2-mem-noc_display/P"slv-qns2-mem-noc_display0 00n00ppslv-qns-mem-noc-hf_display/P#slv-qns-mem-noc-hf_display0 00n00mmqcom,pcie@1c00000 !qcom,pci-msm@@``` ``` `0(parfphydm_coreelbiiatuconfiobars0` ` `0`0F'int_global_intint_aint_bint_cint_d1G1ZDDDDD1h@T4lXB$ UU h4Xt|6x6P1 $(0L45<$J4DpTT;1$;6ptx|f`0d     @ H P XH   D}default  1z7# 17%11*1+1  1OO] 1 m m] 22!2,2B 2R2k22@222>223&&&&&&&&& & & & & &&&pcie0 -- Xx7%2468590Blpcie_0_pipe_clkpcie_0_ref_clk_srcpcie_0_aux_clkpcie_0_cfg_ahb_clkpcie_0_mstr_axi_clkpcie_0_slv_axi_clkpcie_0_ldopcie_0_slv_q2a_axi_clkpcie_tbu_clkpcie_phy_refgen_clkpcie_phy_aux_clk03$!#!pcie_0_core_resetpcie_0_phy_resetpcie_rc0 3217cb:0108qcom,mhi@03217cb:030517cb:0306(mhi --G&6*n*mhi_channelsmhi_chan@0 LOOPBACK*@+++*+8+Jmhi_chan@1 LOOPBACK*@+++*+8+Jmhi_chan@2SAHARA*+++*+8+Jmhi_chan@3SAHARA*+++*+8+Jmhi_chan@4DIAG*@+++*+8+Jmhi_chan@5DIAG*@+++*+8+Jmhi_chan@8QDSS*@+++*+8+Jmhi_chan@9 QDSS*@+++*+8+Jmhi_chan@10 EFS*@+++*+8+Jmhi_chan@11 EFS*@+++*+8+J3:mhi_chan@14QMI0*@+++*+8+Jmhi_chan@15QMI0*@+++*+8+Jmhi_chan@16QMI1*@+++*+8+Jmhi_chan@17QMI1*@+++*+8+Jmhi_chan@18IP_CTRL*@+++*+8+Jmhi_chan@19IP_CTRL*@+++*+8+J+`mhi_chan@20IPCR*@+++*+8+J+Qmhi_chan@21IPCR*@+++*+8+J+`+Qmhi_chan@22TF*@+++*+8+Jmhi_chan@23TF*@+++*+8+Jmhi_chan@25BL*@+++*+8+J+`+Qmhi_chan@26DCI*@+++*+8+Jmhi_chan@27DCI*@+++*+8+Jmhi_chan@32 DUN*@+++*+8+Jmhi_chan@33!DUN*@+++*+8+Jmhi_chan@100dIP_HW0*+++*+8+J3Kmhi_chan@101eIP_HW0*+++*+8+Jmhi_chan@102f IP_HW_ADPL+++*+J3^3omhi_chan@103g IP_HW_QDSS*+++*+8+Jmhi_chan@104hIP_HW_OFFLOAD_0+++*+J3^mhi_chan@105iIP_HW_OFFLOAD_0+++*+J3^3omhi_chan@107k IP_HW_MHIP_1+ ++*+J3^mhi_chan@108l IP_HW_MHIP_1+ ++*+J3^3omhi_eventsmhi_event@0* +o+z+++*mhi_event@1*+o+z++mhi_event@2*+o+z++mhi_event@3*+o+z++mhi_event@4*+o+z3~d++3mhi_event@5*+o+z3~e++33mhi_event@6*+o+z3~f++333mhi_event@7*+o+z3~g++3mhi_event@8*+o+z 3~i++333mhi_event@9*+o+z 3~j++333mhi_event@10*+o+z 3~k++333mhi_event@11*+o+z 3~l++333mhi_devicesmhi_rmnet@03~IP_HW0 3rmnet_mhi33mhi_rmnet@1 3~IP_HW0_RSC33qcom,pcie0_msi@17a00040 !qcom,pci-msi3@F     qcom,pcie@1c08000 !qcom,pci-msm@@ @@ @@@ @0(parfphydm_coreelbiiatuconfiobars0@ @ @0@0F'int_global_intint_aint_bint_cint_d1G1ZD2DDDDl1h @1 $(0L4HXtx|66B 4hUU $T4Xl<5 4Dp`0d J$ptx|f$;6T;1 <5  4Dp`0d J    $ p t x | f $ ; 6 T ; 1    @H3X D}default  1z7f 17h11*1+1  1OO] 1 m m] 22!2,2B 2R 2k 22 @222=223&&~&&&&&&& &  &  &  &  & &&pcie1 dd Xx?%:<>@=A1Blpcie_1_pipe_clkpcie_1_ref_clk_srcpcie_1_aux_clkpcie_1_cfg_ahb_clkpcie_1_mstr_axi_clkpcie_1_slv_axi_clkpcie_1_ldopcie_1_slv_q2a_axi_clkpcie_tbu_clkpcie_phy_refgen_clkpcie_phy_aux_clk03$!#!pcie_1_core_resetpcie_1_phy_resetpcie_rc1 3217cb:0108qcom,mhi@03217cb:030517cb:0306(*n*mhi_channelsmhi_chan@0 LOOPBACK*@+++*+8+Jmhi_chan@1 LOOPBACK*@+++*+8+Jmhi_chan@2SAHARA*+++*+8+Jmhi_chan@3SAHARA*+++*+8+Jmhi_chan@4DIAG*@+++*+8+Jmhi_chan@5DIAG*@+++*+8+Jmhi_chan@8QDSS*@+++*+8+Jmhi_chan@9 QDSS*@+++*+8+Jmhi_chan@10 EFS*@+++*+8+Jmhi_chan@11 EFS*@+++*+8+J3:mhi_chan@14QMI0*@+++*+8+Jmhi_chan@15QMI0*@+++*+8+Jmhi_chan@16QMI1*@+++*+8+Jmhi_chan@17QMI1*@+++*+8+Jmhi_chan@18IP_CTRL*@+++*+8+Jmhi_chan@19IP_CTRL*@+++*+8+J+`mhi_chan@20IPCR*@+++*+8+J+Qmhi_chan@21IPCR*@+++*+8+J+`+Qmhi_chan@22TF*@+++*+8+Jmhi_chan@23TF*@+++*+8+Jmhi_chan@25BL*@+++*+8+J+`+Qmhi_chan@26DCI*@+++*+8+Jmhi_chan@27DCI*@+++*+8+Jmhi_chan@32 DUN*@+++*+8+Jmhi_chan@33!DUN*@+++*+8+Jmhi_chan@100dIP_HW0*+++*+8+J3Kmhi_chan@101eIP_HW0*+++*+8+Jmhi_chan@102f IP_HW_ADPL+++*+J3^3omhi_chan@103g IP_HW_QDSS*+++*+8+Jmhi_chan@104hIP_HW_OFFLOAD_0+++*+Jmhi_chan@105iIP_HW_OFFLOAD_0+++*+J3^3omhi_chan@107k IP_HW_MHIP_1+ ++*+J3^mhi_chan@108l IP_HW_MHIP_1+ ++*+J3^3omhi_eventsmhi_event@0* +o+z+++*mhi_event@1*+o+z++mhi_event@2*+o+z++mhi_event@3*+o+z++mhi_event@4*+o+z3~d++3mhi_event@5*+o+z3~e++33mhi_event@6*+o+z3~f++333mhi_event@7*+o+z3~g++3mhi_event@8*+o+z 3~i++333mhi_event@9*+o+z 3~j++333mhi_event@10*+o+z 3~k++333mhi_event@11*+o+z 3~l++333mhi_devicesmhi_rmnet@03~IP_HW0 3rmnet_mhi33mhi_rmnet@1 3~IP_HW0_RSC33qcom,pcie1_msi@17a00040 !qcom,pci-msi3@F !"#$%&'()*+,-./0123456789:;<=>?qcom,pcie1_edma@40002000!qcom,pci-edma(@ FD V pci-edma-intqcom,pcie@40004000 !qcom,pcie-ep@@@@@ @@ 0 )msidm_coreelbiiatuedmaparfphymmioF1G1ZD2 int_global}default  37g 1z7f 17h11*1+1  1OO] 1 m m] 2@x?<>@:=BA|lpcie_pipe_clkpcie_cfg_ahb_clkpcie_mstr_axi_clkpcie_slv_axi_clkpcie_aux_clkpcie_ldopcie_sleep_clkpcie_slv_q2a_axi_clk!!pcie_core_resetpcie_phy_resetpcie-ep dd 4244/4D 4X @ LPXt6x6|B  $XlVxT14DpJ$ptx|v$97T914DpJ    $  p t x | v $   9 7  T  9 1  V    @HxPX  D4f &4r 4disabledmhi_dev@1c0b000!qcom,msm-mhi-devmhi_mmio_base44444txrx mhi-device-inta44 4disabledqcom,smp2p-modem@1799000c !qcom,smp2p4  44#hmaster-kernel5 master-kernel5wwslave-kernel 5 slave-kernelvvqcom,smp2p-ipa-1-out5 ipa5qcom,smp2p-ipa-1-in5 ipaqcom,smp2p-wlan-1-in5 wlanqcom,smp2p-adsp@1799000c !qcom,smp2p4  4 4#hmaster-kernel5 master-kernel5zzslave-kernel 5 slave-kernelyyqcom,smp2p-rdbg2-out5 rdbg5--qcom,smp2p-rdbg2-in5 rdbg..qcom,smp2p-dsps@1799000c !qcom,smp2p4  44#hmaster-kernel5 master-kernel5~~slave-kernel 5 slave-kernel}}sleepstate-out 5 sleepstate5qcom,sleepstate-in5 sleepstate_seeqcom,smp2p-cdsp@1799000c !qcom,smp2p4^ @ 44#hmaster-kernel5 master-kernel5slave-kernel 5 slave-kernelqcom,smp2p-rdbg5-out5 rdbg5//qcom,smp2p-rdbg5-in5 rdbg00qcom,smp2p-qvrexternal5-out 5 qvrexternal5BBreplicator@6046000!arm,primecell50 `replicator-base5Gcoresight-replicator-qdssxC lapb_pclkportsport@0endpoint5Vport@1endpoint5Vport@2endpoint5f5Vreplicator@604A000!arm,primecell50 replicator-base5Gcoresight-replicator-qdss1xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vreplicator@6b0a000!arm,primecell50 replicator-base5Gcoresight-replicator-swaoxC lapb_pclkportsport@0endpoint5V##port@1endpoint5Vport@2endpoint5f5Vtmc@6b09000!arm,primecell50a tmc-base5Gcoresight-tmc-etf-swao5qxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vfunnel@0x6b08000!arm,primecell50 funnel-base5Gcoresight-funnel-swaoxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5V&&port@2endpoint5f5Vport@3endpoint5f5Vtpda@6b01000!arm,primecell50i tpda-base5Gcoresight-tpda-swao5G5 5@xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vtpdm@6b02000!arm,primecell50h  tpdm-base5Gcoresight-tpdm-swao-0xC lapb_pclkportendpoint5Vtpdm@6b03000!arm,primecell50h0 tpdm-base5Gcoresight-tpdm-swao-1xC lapb_pclk5portendpoint5Vtmc@6048000!arm,primecell50a@Ptmc-basebam-base&&5@5Gcoresight-tmc-etr55qxC lapb_pclk byte-cntr-irqportendpoint5f5Vtmc@6047000!arm,primecell50ap tmc-base5Gcoresight-tmc-etf55q5xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vfunnel@6045000!arm,primecell50P funnel-base5Gcoresight-funnel-mergxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vport@3endpoint5f5Vstm@6002000!arm,primecell50b (x ,stm-basestm-stimulus-basestm-debug-status5Gcoresight-stmxC lapb_pclkportendpoint5Vhwevent@0x091866F0!qcom,coresight-hwevent@ f f `8 `84 PP Pddr-ch0-cfgddr-ch23-cfgddr-ch0-ctrlddr-ch23-ctrlapss-testbus-mux-cfgapss-rsc-hwevent-mux0-selectgpu-rsc-hwevent-mux0-selectsde-rsc-hwevent-mux0-select5Gcoresight-hwevent5qxC lapb_pclkcsr@0x6001000!qcom,coresight-csr csr-base5Gcoresight-csr56 6"6=csr@6b0e000!qcom,coresight-csr csr-base5Gcoresight-swao-csr6KxC lapb_pclk6=funnel@0x6041000!arm,primecell50 funnel-base5Gcoresight-funnel-in0xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vport@3endpoint5f5Vfunnel@0x6042000!arm,primecell50  funnel-base5Gcoresight-funnel-in1xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5V$$port@3endpoint5f5Vport@4endpoint5f5Vfunnel@0x6043000!arm,primecell500 funnel-base5Gcoresight-funnel-in2xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5V''port@2endpoint5f5Vport@3endpoint5f5Vfunnel@0x6943000!arm,primecell500 funnel-base5Gcoresight-funnel-gfxxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vtpda@6004000!arm,primecell50i@ tpda-base5Gcoresight-tpda5A6b 6t @5      5@@ @ @xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5V  port@2endpoint5f5V  port@3endpoint5f5Vport@4endpoint5f5Vport@5endpoint5f5Vport@6endpoint5f5Vport@7endpoint5f5Vport@8 endpoint5f5Vport@9 endpoint5f5Vport@10endpoint5f5Vtpda@6832000!arm,primecell50i  tpda-base5Gcoresight-tpda-modem5C5 5@xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vtpdm@6830000!arm,primecell50h tpdm-base5Gcoresight-tpdm-modemxC lapb_pclkportendpoint5Vfunnel@6846000!arm,primecell50` funnel-base5Gcoresight-funnel-lpassxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vfunnel_1@6846000!arm,primecell50p `#funnel-base-dummyfunnel-base-real5Gcoresight-funnel-lpass-1xC lapb_pclk6portsport@0endpoint5Vport@1endpoint5f5V%%tpdm@6844000!arm,primecell50h@ tpdm-base5Gcoresight-tpdm-lpassxC lapb_pclk5portendpoint5Vtpdm@6c28000!arm,primecell50h€ tpdm-base5Gcoresight-tpdm-centerxC lapb_pclk5portendpoint5Vtpdm@6ac0000!arm,primecell50h tpdm-base5Gcoresight-tpdm-dl-northxC lapb_pclk5portendpoint5Vtpda@6ac1000!arm,primecell50i tpda-base5Gcoresight-tpda-dl-north5a5 xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vfunnel@69c2000!arm,primecell50  funnel-base5Gcoresight-funnel-dl-southxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vtpdm@69c0000!arm,primecell50h tpdm-base5Gcoresight-tpdm-dl-southxC lapb_pclkportendpoint5Vfunnel@6ac2000!arm,primecell50  funnel-base5Gcoresight-funnel-dl-northxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vtpdm@699c000!qcom,coresight-dummy5Gcoresight-tpdm-wcss6portendpoint5Vtpdm@684c000!arm,primecell50h tpdm-base5Gcoresight-tpdm-prngxC lapb_pclkportendpoint5Vfunnel@6883000!arm,primecell500 funnel-base5Gcoresight-funnel-spssxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vtpda@6882000!arm,primecell50i  tpda-base5Gcoresight-tpda-spss5F5 xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vtpdm@6880000!arm,primecell50h tpdm-base5Gcoresight-tpdm-spssxC lapb_pclkportendpoint5Vspss_etm0!qcom,coresight-dummy5Gcoresight-spss-etm06portendpoint5Vtpdm@69d0000!arm,primecell50h tpdm-base5Gcoresight-tpdm-qmxC lapb_pclkportendpoint5V  tpda@7862000!arm,primecell50i  tpda-base5Gcoresight-tpda-apss5B5 xC lapb_pclkportsport@0endpoint5V,,port@1endpoint5f5Vtpdm@7860000!arm,primecell50h tpdm-base5Gcoresight-tpdm-apssxC lapb_pclkportendpoint5Vtpda@78c0000!arm,primecell50i tpda-base5Gcoresight-tpda-llm-silver5H5 xC lapb_pclkportsport@0endpoint5V**port@1endpoint5f5Vtpdm@78a0000!arm,primecell50h tpdm-base5Gcoresight-tpdm-llm-silverxC lapb_pclkportendpoint5Vtpda@78d0000!arm,primecell50i tpda-base5Gcoresight-tpda-llm-gold5I5 xC lapb_pclkportsport@0endpoint5V++port@1endpoint5f5V  tpdm@78b0000!arm,primecell50h tpdm-base5Gcoresight-tpdm-llm-goldxC lapb_pclkportendpoint5V funnel@6c0b000!arm,primecell50 funnel-base5Gcoresight-funnel-dl-mmxC lapb_pclkportsport@0endpoint5V port@1endpoint5f5V funnel_1@6c0b000!arm,primecell50p#funnel-base-dummyfunnel-base-real5Gcoresight-funnel-dl-mm1xC lapb_pclk6portsport@0endpoint5V port@1endpoint5f5V tpdm@6c08000!arm,primecell50h tpdm-base5Gcoresight-tpdm-mmxC lapb_pclk5portendpoint5V  funnel@6861000!arm,primecell50 funnel-base5Gcoresight-funnel-turingxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vfunnel_1@6861000!arm,primecell50p#funnel-base-dummyfunnel-base-real5Gcoresight-funnel-turing-1xC lapb_pclk6portsport@0endpoint5V  port@1endpoint5f5V""tpdm@6860000!arm,primecell50h tpdm-base5Gcoresight-tpdm-turingxC lapb_pclk5portendpoint5Vfunnel@6a05000!arm,primecell50P funnel-base5Gcoresight-funnel-ddr-0xC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vtpdm@6A00000!arm,primecell50h tpdm-base5Gcoresight-tpdm-ddrxC lapb_pclk5portendpoint5Vtpdm@6850000!arm,primecell50h tpdm-base5Gcoresight-tpdm-pimemxC lapb_pclkportendpoint5Vtpdm@6840000!arm,primecell50h tpdm-base5Gcoresight-tpdm-vsensexC lapb_pclkportendpoint5Vtpda@7832000!arm,primecell50i  tpda-base5Gcoresight-tpda-olc5E5@xC lapb_pclkportsport@0endpoint5V))port@1endpoint5f5Vtpdm@7830000!arm,primecell50h tpdm-base5Gcoresight-tpdm-olcxC lapb_pclkportendpoint5Vtpdm@6980000!arm,primecell50h tpdm-base5Gcoresight-tpdm-npu@xC/*pp p p p zlapb_pclkgcc_npu_trig_clkgcc_npu_at_clknpu_core_apb_clknpu_core_atb_clknpu_core_clknpu_core_clk_srcnpu_core_cti_clkq6gcc_npu_trig_clkgcc_npu_at_clknpu_core_apb_clknpu_core_atb_clknpu_core_clknpu_core_clk_srcnpu_core_cti_clkiY  6vddvdd_cxportendpoint5Vfunnel@6005000!arm,primecell50P funnel-base5Gcoresight-funnel-qatbxC lapb_pclkportsport@0endpoint5Vport@1endpoint5f5Vport@2endpoint5f5Vport@3endpoint5f5V cti@78e0000!arm,primecell50f cti-base5Gcoresight-cti-apss_cti0xC lapb_pclkcti@78f0000!arm,primecell50f cti-base5Gcoresight-cti-apss_cti1xC lapb_pclkcti@7900000!arm,primecell50f cti-base5Gcoresight-cti-apss_cti2xC lapb_pclkcti@6a02000!arm,primecell50f  cti-base5Gcoresight-cti-ddr_dl_0_cti_0xC lapb_pclkcti@6a03000!arm,primecell50f0 cti-base5Gcoresight-cti-ddr_dl_0_cti_1xC lapb_pclkcti@6a10000!arm,primecell50f cti-base5Gcoresight-cti-ddr_dl_1_cti_0xC lapb_pclkcti@6a11000!arm,primecell50f cti-base5Gcoresight-cti-ddr_dl_1_cti_1xC lapb_pclkcti@6c09000!arm,primecell50f cti-base5Gcoresight-cti-dlmm_cti0xC lapb_pclkcti@6c0a000!arm,primecell50f cti-base5Gcoresight-cti-dlmm_cti1xC lapb_pclkcti@6c29000!arm,primecell50f cti-base5Gcoresight-cti-dlct_cti0xC lapb_pclkcti@6c2a000!arm,primecell50f  cti-base5Gcoresight-cti-dlct_cti1xC lapb_pclkcti@6010000!arm,primecell50f cti-base5Gcoresight-cti0xC lapb_pclkcti@6011000!arm,primecell50f cti-base5Gcoresight-cti1xC lapb_pclkcti@6012000!arm,primecell50f  cti-base5Gcoresight-cti2xC lapb_pclk6}cti-trigout-pctrl!cti@6013000!arm,primecell50f0 cti-base5Gcoresight-cti3xC lapb_pclkcti@6014000!arm,primecell50f@ cti-base5Gcoresight-cti4xC lapb_pclkcti@6015000!arm,primecell50fP cti-base5Gcoresight-cti5xC lapb_pclkcti@6016000!arm,primecell50f` cti-base5Gcoresight-cti6xC lapb_pclkcti@6017000!arm,primecell50fp cti-base5Gcoresight-cti7xC lapb_pclkcti@6018000!arm,primecell50f cti-base5Gcoresight-cti8xC lapb_pclkcti@6019000!arm,primecell50f cti-base5Gcoresight-cti9xC lapb_pclk  cti@601a000!arm,primecell50f cti-base5Gcoresight-cti10xC lapb_pclk  cti@601b000!arm,primecell50f cti-base5Gcoresight-cti11xC lapb_pclk  cti@601c000!arm,primecell50f cti-base5Gcoresight-cti12xC lapb_pclk  cti@601d000!arm,primecell50f cti-base5Gcoresight-cti13xC lapb_pclk  cti@601e000!arm,primecell50f cti-base5Gcoresight-cti14xC lapb_pclkcti@601f000!arm,primecell50f cti-base5Gcoresight-cti15xC lapb_pclkcti@7020000!arm,primecell50f cti-base5Gcoresight-cti-cpu0xC lapb_pclkcti@7120000!arm,primecell50f cti-base5Gcoresight-cti-cpu1xC lapb_pclkcti@7220000!arm,primecell50f" cti-base5Gcoresight-cti-cpu2xC lapb_pclkcti@7320000!arm,primecell50f2 cti-base5Gcoresight-cti-cpu3xC lapb_pclkcti@7420000!arm,primecell50fB cti-base5Gcoresight-cti-cpu4xC lapb_pclkcti@7520000!arm,primecell50fR cti-base5Gcoresight-cti-cpu5xC lapb_pclkcti@7620000!arm,primecell50fb cti-base5Gcoresight-cti-cpu6xC lapb_pclkcti@7720000!arm,primecell50fr cti-base5Gcoresight-cti-cpu7xC lapb_pclkcti@6b04000!arm,primecell50f@ cti-base5Gcoresight-cti-swao_cti0xC lapb_pclktgu@6b0c000!arm,primecell50 tgu-base66675Gcoresight-tgu-ipcbxC lapb_pclkturing_etm0!qcom,coresight-remote-etm5Gcoresight-turing-etm07 portendpoint5V"dummy_sink!qcom,coresight-dummy5Gcoresight-eud7$portendpoint5f5V#modem_etm0!qcom,coresight-remote-etm5Gcoresight-modem-etm07portendpoint5V$audio_etm0!qcom,coresight-remote-etm5Gcoresight-audio-etm07portendpoint5V%ssc_etm0!qcom,coresight-remote-etm5Gcoresight-ssc-etm07portendpoint5V&funnel@7810000!arm,primecell50 funnel-base5Gcoresight-funnel-apss-mergxC lapb_pclkportsport@0endpoint5V'port@1endpoint5f5V(55port@2endpoint5f5V)port@3endpoint5f5V*port@4endpoint5f5V+port@5endpoint5f5V,etm@7040000!arm,primecell50 ]745Gcoresight-etm0xC lapb_pclkportendpoint5V-66etm@7140000!arm,primecell50 ]745Gcoresight-etm1xC lapb_pclkportendpoint5V.77etm@7240000!arm,primecell50 ]$745Gcoresight-etm2xC lapb_pclkportendpoint5V/88etm@7340000!arm,primecell50 ]4745Gcoresight-etm3xC lapb_pclkportendpoint5V099etm@7440000!arm,primecell50 ]D745Gcoresight-etm4xC lapb_pclk  portendpoint5V1::etm@7540000!arm,primecell50 ]T745Gcoresight-etm5xC lapb_pclk!!portendpoint5V2;;etm@7640000!arm,primecell50 ]d745Gcoresight-etm6xC lapb_pclk""portendpoint5V3<<etm@7740000!arm,primecell50 ]t745Gcoresight-etm7xC lapb_pclk##portendpoint5V4==funnel@7800000!arm,primecell50 funnel-base5Gcoresight-funnel-apssxC lapb_pclk$$portsport@0endpoint5V5((port@1endpoint5f5V6--port@2endpoint5f5V7..port@3endpoint5f5V8//port@4endpoint5f5V900port@5endpoint5f5V:11port@6endpoint5f5V;22port@7endpoint5f5V<33port@8endpoint5f5V=44apps-smmu@0x15000000!qcom,qsmmu-v500 basetcu-base7G7T7c7y7Aabcdefghijklmnopqrstuv;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXY apps_smmu) ssH7 &&anoc_1_tbu@0x15185000!qcom,qsmmuv500-tbuP"basestatus-reg77vdd> apps_smmu) ss%%anoc_2_tbu@0x15189000!qcom,qsmmuv500-tbu"basestatus-reg77vdd? apps_smmu) ss&&mnoc_hf_1_tbu@0x15191000!qcom,qsmmuv500-tbu"basestatus-reg7 7vdd@mnoc_hf_1_tbu) ''compute_dsp_0_tbu@0x15199000!qcom,qsmmuv500-tbu"(basestatus-reg7 apps_smmu) 'V'V((mnoc_hf_0_tbu@0x1518d000!qcom,qsmmuv500-tbu"basestatus-reg77vddAmnoc_hf_0_tbu) ))compute_dsp_1_tbu@0x15195000!qcom,qsmmuv500-tbuP" basestatus-reg7 apps_smmu) 'V'V**adsp_tbu@0x1519d000!qcom,qsmmuv500-tbu"0basestatus-reg77vddB apps_smmu) ss++anoc_1_pcie_tbu@0x151a1000!qcom,qsmmuv500-tbu"8basestatus-reg777vddClgcc_aggre_noc_pcie_tbu_clkx apps_smmu) ss,,mnoc_sf_0_tbu@0x151a5000!qcom,qsmmuv500-tbuP"@basestatus-reg7 7vddDmnoc_sf_0_tbu) --kgsl_iommu_test_device!iommu-debug-test Ekgsl_iommu_coherent_test_device!iommu-debug-test E "apps_iommu_test_device!iommu-debug-test &!apps_iommu_coherent_test_device!iommu-debug-test &#"qcom,qupv3_0_geni_se@8c0000!qcom,qupv3-geni-se`77(@IIqcom,iommu_qupv3_0_geni_se_cb!qcom,qupv3-geni-se-cb &..i2c@880000!qcom,i2c-geni@ Ylse-clkm-ahbs-ahbxQyz04F@F@4txrx}defaultsleepGH8 I 4disabled//i2c@884000!qcom,i2c-geni@@ Zlse-clkm-ahbs-ahbxSyz04F@F@4txrx}defaultsleepJK8 I 4disabled00i2c@888000!qcom,i2c-geni@ [lse-clkm-ahbs-ahbxUyz04F@F@4txrx}defaultsleepLM8 I 4disabled11i2c@88c000!qcom,i2c-geni@ \lse-clkm-ahbs-ahbxWyz04F@F@4txrx}defaultsleepNO8 I 4disabled22i2c@890000!qcom,i2c-geni@ ]lse-clkm-ahbs-ahbxYyz04F@F@4txrx}defaultsleepPQ8 I4ok33fsa4480@43!qcom,fsa4480-i2cC}defaultRi2c@894000!qcom,i2c-geni@@ ^lse-clkm-ahbs-ahbx[yz04F@F@4txrx}defaultsleepST8 I 4disabled44i2c@898000!qcom,i2c-geni@ _lse-clkm-ahbs-ahbx]yz04F@F@4txrx}defaultsleepUV8 I 4disabled55i2c@89c000!qcom,i2c-geni@ `lse-clkm-ahbs-ahbx_yz04F@F@4txrx}defaultsleepWX8 I 4disabled66spi@880000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxQyz}defaultsleepYZ Y88 I04F@F@4txrx 4disabled77spi@884000!qcom,spi-geni@@se_physlse-clkm-ahbs-ahbxSyz}defaultsleep[\ Z88 I04F@F@4txrx 4disabled88spi@888000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxUyz}defaultsleep]^ [88 I04F@F@4txrx 4disabled99spi@88c000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxWyz}defaultsleep_`a \88 I04F@F@4txrx 4disabled::spi@890000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxYyz}defaultsleepbc ]88 I04F@F@4txrx 4disabled;;spi@894000!qcom,spi-geni@@se_physlse-clkm-ahbs-ahbx[yz}defaultsleepde ^88 I04F@F@4txrx 4disabled<<spi@898000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbx]yz}defaultsleepfg _88 I04F@F@4txrx 4disabled==spi@89c000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbx_yz}defaultsleephi `88 I04F@F@4txrx 4disabled>>qcom,qupv3_1_geni_se@ac0000!qcom,qupv3-geni-se`77(@llqcom,iommu_qupv3_1_geni_se_cb!qcom,qupv3-geni-se-cb &??qcom,qup_uart@0xa90000!qcom,msm-geni-console@se_physlse-clkm-ahbs-ahbxi{|}defaultsleepjk e8 l 4disabled@@qcom,qup_uart@0xc8c000!qcom,msm-geni-serial-hs@se_physlse-clkm-ahbs-ahbxs}~}defaultactivesleepmn opq ,opqI7.8 r80 4disabledAAi2c@a80000!qcom,i2c-geni@ alse-clkm-ahbs-ahbxa{|04s@s@4txrx}defaultsleeptu8 l 4disabledBBi2c@a84000!qcom,i2c-geni@@ blse-clkm-ahbs-ahbxc{|04s@s@4txrx}defaultsleepvw8 l 4disabledCCi2c@a88000!qcom,i2c-geni@ clse-clkm-ahbs-ahbxe{|04s@s@4txrx}defaultsleepxy8 l 4disabledDDi2c@a8c000!qcom,i2c-geni@ dlse-clkm-ahbs-ahbxg{|04s@s@4txrx}defaultsleepz{8 l 4disabledEEi2c@a90000!qcom,i2c-geni@ else-clkm-ahbs-ahbxi{|04s@s@4txrx}defaultsleep|}8 l 4disabledFFi2c@c8c000!qcom,i2c-geni@ Ilse-clkm-ahbs-ahbxs}~04~@~@4txrx}defaultsleep8 r 4disabledGGspi@a80000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxa{|}defaultsleep a88 l04s@s@4txrx 4disabledHHspi@a84000!qcom,spi-geni@@se_physlse-clkm-ahbs-ahbxc{|}defaultsleep b88 l04s@s@4txrx 4disabledIIspi@a88000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxe{|}defaultsleep c88 l04s@s@4txrx 4disabledJJspi@a8c000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxg{|}defaultsleep d88 l04s@s@4txrx 4disabledKKspi@a90000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxi{|}defaultsleep e88 l04s@s@4txrx 4disabledLLspi@c8c000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxs}~}defaultsleep I88 l04~@~@4txrx 4disabledMMqcom,qupv3_2_geni_se@cc0000!qcom,qupv3-geni-se`77(@rrqcom,iommu_qupv3_2_geni_se_cb!qcom,qupv3-geni-se-cb &NNi2c@0xc90000!qcom,i2c-geni@ Jlse-clkm-ahbs-ahbxu}~04~@~@4txrx}defaultsleep8 r 4disabledOOi2c@0xc94000!qcom,i2c-geni@@ Klse-clkm-ahbs-ahbxw}~04~@~@4txrx}defaultsleep8 r 4disabledPPi2c@0xa94000!qcom,i2c-geni@@ flse-clkm-ahbs-ahbxk{|04~@~@4txrx}defaultsleep8 l 4disabledQQi2c@0xc80000!qcom,i2c-geni@ ulse-clkm-ahbs-ahbxm}~04~@~@4txrx}defaultsleep8 r 4disabledRRi2c@0xc84000!qcom,i2c-geni@@ Glse-clkm-ahbs-ahbxo}~04~@~@4txrx}defaultsleep8 r 4disabledSSi2c@0xc88000!qcom,i2c-geniȀ@ Hlse-clkm-ahbs-ahbxq}~04~@~@4txrx}defaultsleep8 r 4disabledTTspi@c90000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxw}~}defaultsleep K88 r04~@~@4txrx 4disabledUUspi@a94000!qcom,spi-geni@@se_physlse-clkm-ahbs-ahbxk{|}defaultsleep f88 l04s@s@4txrx 4disabledVVspi@c80000!qcom,spi-geni@se_physlse-clkm-ahbs-ahbxm}~}defaultsleep u88 r04~@~@4txrx 4disabledWWspi@c84000!qcom,spi-geni@@se_physlse-clkm-ahbs-ahbxo}~}defaultsleep G88 r04~@~@4txrx 4disabledXXspi@c88000!qcom,spi-geniȀ@se_physlse-clkm-ahbs-ahbxq}~}defaultsleep H88 r04~@~@4txrx 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/soc/pinctrl@03000000/tert_aux_pcm/tert_aux_pcm_sleep7c/soc/pinctrl@03000000/tert_aux_pcm/tert_aux_pcm_active>c0/soc/pinctrl@03000000/tert_aux_pcm_din/tert_aux_pcm_din_sleep?cG/soc/pinctrl@03000000/tert_aux_pcm_din/tert_aux_pcm_din_active@c_/soc/pinctrl@03000000/tert_aux_pcm_dout/tert_aux_pcm_dout_sleepAcw/soc/pinctrl@03000000/tert_aux_pcm_dout/tert_aux_pcm_dout_active6c/soc/pinctrl@03000000/quat_aux_pcm/quat_aux_pcm_sleep7c/soc/pinctrl@03000000/quat_aux_pcm/quat_aux_pcm_active>c/soc/pinctrl@03000000/quat_aux_pcm_din/quat_aux_pcm_din_sleep?c/soc/pinctrl@03000000/quat_aux_pcm_din/quat_aux_pcm_din_active@c/soc/pinctrl@03000000/quat_aux_pcm_dout/quat_aux_pcm_dout_sleepAc/soc/pinctrl@03000000/quat_aux_pcm_dout/quat_aux_pcm_dout_active<d/soc/pinctrl@03000000/pri_aux_pcm_clk/pri_aux_pcm_clk_sleep=d-/soc/pinctrl@03000000/pri_aux_pcm_clk/pri_aux_pcm_clk_active>dD/soc/pinctrl@03000000/pri_aux_pcm_sync/pri_aux_pcm_sync_sleep?d[/soc/pinctrl@03000000/pri_aux_pcm_sync/pri_aux_pcm_sync_active<ds/soc/pinctrl@03000000/pri_aux_pcm_din/pri_aux_pcm_din_sleep=d/soc/pinctrl@03000000/pri_aux_pcm_din/pri_aux_pcm_din_active>d/soc/pinctrl@03000000/pri_aux_pcm_dout/pri_aux_pcm_dout_sleep?d/soc/pinctrl@03000000/pri_aux_pcm_dout/pri_aux_pcm_dout_active6d/soc/pinctrl@03000000/quin_aux_pcm/quin_aux_pcm_sleep7d/soc/pinctrl@03000000/quin_aux_pcm/quin_aux_pcm_active>d/soc/pinctrl@03000000/quin_aux_pcm_din/quin_aux_pcm_din_sleep?e /soc/pinctrl@03000000/quin_aux_pcm_din/quin_aux_pcm_din_active@e%/soc/pinctrl@03000000/quin_aux_pcm_dout/quin_aux_pcm_dout_sleepAe=/soc/pinctrl@03000000/quin_aux_pcm_dout/quin_aux_pcm_dout_active,eV/soc/pinctrl@03000000/sec_tdm/sec_tdm_sleep-ed/soc/pinctrl@03000000/sec_tdm/sec_tdm_active4es/soc/pinctrl@03000000/sec_tdm_din/sec_tdm_din_sleep5e/soc/pinctrl@03000000/sec_tdm_din/sec_tdm_din_active6e/soc/pinctrl@03000000/sec_tdm_dout/sec_tdm_dout_sleep7e/soc/pinctrl@03000000/sec_tdm_dout/sec_tdm_dout_active.e/soc/pinctrl@03000000/tert_tdm/tert_tdm_sleep/e/soc/pinctrl@03000000/tert_tdm/tert_tdm_active6e/soc/pinctrl@03000000/tert_tdm_din/tert_tdm_din_sleep7e/soc/pinctrl@03000000/tert_tdm_din/tert_tdm_din_active8f/soc/pinctrl@03000000/tert_tdm_dout/tert_tdm_dout_sleep9f/soc/pinctrl@03000000/tert_tdm_dout/tert_tdm_dout_active.f./soc/pinctrl@03000000/quat_tdm/quat_tdm_sleep/f=/soc/pinctrl@03000000/quat_tdm/quat_tdm_active6fM/soc/pinctrl@03000000/quat_tdm_din/quat_tdm_din_sleep7f`/soc/pinctrl@03000000/quat_tdm_din/quat_tdm_din_active8ft/soc/pinctrl@03000000/quat_tdm_dout/quat_tdm_dout_sleep9f/soc/pinctrl@03000000/quat_tdm_dout/quat_tdm_dout_active4f/soc/pinctrl@03000000/pri_tdm_clk/pri_tdm_clk_sleep5f/soc/pinctrl@03000000/pri_tdm_clk/pri_tdm_clk_active6f/soc/pinctrl@03000000/pri_tdm_sync/pri_tdm_sync_sleep7f/soc/pinctrl@03000000/pri_tdm_sync/pri_tdm_sync_active4f/soc/pinctrl@03000000/pri_tdm_din/pri_tdm_din_sleep5f/soc/pinctrl@03000000/pri_tdm_din/pri_tdm_din_active6g/soc/pinctrl@03000000/pri_tdm_dout/pri_tdm_dout_sleep7g!/soc/pinctrl@03000000/pri_tdm_dout/pri_tdm_dout_active.g5/soc/pinctrl@03000000/quin_tdm/quin_tdm_sleep/gD/soc/pinctrl@03000000/quin_tdm/quin_tdm_active6gT/soc/pinctrl@03000000/quin_tdm_din/quin_tdm_din_sleep7gg/soc/pinctrl@03000000/quin_tdm_din/quin_tdm_din_active8g{/soc/pinctrl@03000000/quin_tdm_dout/quin_tdm_dout_sleep9g/soc/pinctrl@03000000/quin_tdm_dout/quin_tdm_dout_active8g/soc/pinctrl@03000000/sec_mi2s_mclk/sec_mi2s_mclk_sleep9g/soc/pinctrl@03000000/sec_mi2s_mclk/sec_mi2s_mclk_active.g/soc/pinctrl@03000000/sec_mi2s/sec_mi2s_sleep/g/soc/pinctrl@03000000/sec_mi2s/sec_mi2s_active6g/soc/pinctrl@03000000/sec_mi2s_sd0/sec_mi2s_sd0_sleep7g/soc/pinctrl@03000000/sec_mi2s_sd0/sec_mi2s_sd0_active6h/soc/pinctrl@03000000/sec_mi2s_sd1/sec_mi2s_sd1_sleep7h&/soc/pinctrl@03000000/sec_mi2s_sd1/sec_mi2s_sd1_active:h:/soc/pinctrl@03000000/tert_mi2s_mclk/tert_mi2s_mclk_sleep;hO/soc/pinctrl@03000000/tert_mi2s_mclk/tert_mi2s_mclk_active0he/soc/pinctrl@03000000/tert_mi2s/tert_mi2s_sleep1hu/soc/pinctrl@03000000/tert_mi2s/tert_mi2s_active8h/soc/pinctrl@03000000/tert_mi2s_sd0/tert_mi2s_sd0_sleep9h/soc/pinctrl@03000000/tert_mi2s_sd0/tert_mi2s_sd0_active8h/soc/pinctrl@03000000/tert_mi2s_sd1/tert_mi2s_sd1_sleep9h/soc/pinctrl@03000000/tert_mi2s_sd1/tert_mi2s_sd1_active:h/soc/pinctrl@03000000/quat_mi2s_mclk/quat_mi2s_mclk_sleep;h/soc/pinctrl@03000000/quat_mi2s_mclk/quat_mi2s_mclk_active0i/soc/pinctrl@03000000/quat_mi2s/quat_mi2s_sleep1i/soc/pinctrl@03000000/quat_mi2s/quat_mi2s_active8i$/soc/pinctrl@03000000/quat_mi2s_sd0/quat_mi2s_sd0_sleep9i8/soc/pinctrl@03000000/quat_mi2s_sd0/quat_mi2s_sd0_active8iM/soc/pinctrl@03000000/quat_mi2s_sd1/quat_mi2s_sd1_sleep9ia/soc/pinctrl@03000000/quat_mi2s_sd1/quat_mi2s_sd1_active8iv/soc/pinctrl@03000000/quat_mi2s_sd2/quat_mi2s_sd2_sleep9i/soc/pinctrl@03000000/quat_mi2s_sd2/quat_mi2s_sd2_active8i/soc/pinctrl@03000000/quat_mi2s_sd3/quat_mi2s_sd3_sleep9i/soc/pinctrl@03000000/quat_mi2s_sd3/quat_mi2s_sd3_active8i/soc/pinctrl@03000000/pri_mi2s_mclk/pri_mi2s_mclk_sleep9i/soc/pinctrl@03000000/pri_mi2s_mclk/pri_mi2s_mclk_active6i/soc/pinctrl@03000000/pri_mi2s_sck/pri_mi2s_sck_sleep7j/soc/pinctrl@03000000/pri_mi2s_sck/pri_mi2s_sck_active4j/soc/pinctrl@03000000/pri_mi2s_ws/pri_mi2s_ws_sleep5j*/soc/pinctrl@03000000/pri_mi2s_ws/pri_mi2s_ws_active6j=/soc/pinctrl@03000000/pri_mi2s_sd0/pri_mi2s_sd0_sleep7jP/soc/pinctrl@03000000/pri_mi2s_sd0/pri_mi2s_sd0_active6jd/soc/pinctrl@03000000/pri_mi2s_sd1/pri_mi2s_sd1_sleep7jw/soc/pinctrl@03000000/pri_mi2s_sd1/pri_mi2s_sd1_active:j/soc/pinctrl@03000000/quin_mi2s_mclk/quin_mi2s_mclk_sleep;j/soc/pinctrl@03000000/quin_mi2s_mclk/quin_mi2s_mclk_active0j/soc/pinctrl@03000000/quin_mi2s/quin_mi2s_sleep1j/soc/pinctrl@03000000/quin_mi2s/quin_mi2s_active8j/soc/pinctrl@03000000/quin_mi2s_sd0/quin_mi2s_sd0_sleep9j/soc/pinctrl@03000000/quin_mi2s_sd0/quin_mi2s_sd0_active8k/soc/pinctrl@03000000/quin_mi2s_sd1/quin_mi2s_sd1_sleep9k/soc/pinctrl@03000000/quin_mi2s_sd1/quin_mi2s_sd1_activek)/soc/pinctrl@03000000/pmx_sde-k1/soc/pinctrl@03000000/pmx_sde/sde_dsi_active.k@/soc/pinctrl@03000000/pmx_sde/sde_dsi_suspend.kP/soc/pinctrl@03000000/pmx_sde/sde_dsi1_active/k`/soc/pinctrl@03000000/pmx_sde/sde_dsi1_suspend/kq/soc/pinctrl@03000000/pmx_sde_te/sde_te_active0k/soc/pinctrl@03000000/pmx_sde_te/sde_te_suspend0k/soc/pinctrl@03000000/pmx_sde_te/sde_te1_active1k/soc/pinctrl@03000000/pmx_sde_te/sde_te1_suspend/k/soc/pinctrl@03000000/sde_dp_usbplug_cc_active0k/soc/pinctrl@03000000/sde_dp_usbplug_cc_suspend+k/soc/pinctrl@03000000/ap2mdm/ap2mdm_active*k/soc/pinctrl@03000000/ap2mdm/ap2mdm_sleep+k/soc/pinctrl@03000000/mdm2ap/mdm2ap_active*l /soc/pinctrl@03000000/mdm2ap/mdm2ap_sleep<l/soc/pinctrl@03000000/fsa_usbc_ana_en_n@100/fsa_usbc_ana_en.l&/soc/pinctrl@03000000/cam_sensor_mclk0_active/l>/soc/pinctrl@03000000/cam_sensor_mclk0_suspend.lW/soc/pinctrl@03000000/cam_sensor_mclk1_active/lo/soc/pinctrl@03000000/cam_sensor_mclk1_suspend.l/soc/pinctrl@03000000/cam_sensor_mclk2_active/l/soc/pinctrl@03000000/cam_sensor_mclk2_suspend.l/soc/pinctrl@03000000/cam_sensor_mclk3_active/l/soc/pinctrl@03000000/cam_sensor_mclk3_suspend/l/soc/pinctrl@03000000/cam_sensor_eldo2_default,m/soc/pinctrl@03000000/camera_vaf_en_default-m/soc/pinctrl@03000000/camera_vana_en_default-m0/soc/pinctrl@03000000/cam_sensor_active_rear.mG/soc/pinctrl@03000000/cam_sensor_suspend_rear1m_/soc/pinctrl@03000000/cam_sensor_active_rear_aux2mz/soc/pinctrl@03000000/cam_sensor_suspend_rear_aux.m/soc/pinctrl@03000000/cam_sensor_active_front/m/soc/pinctrl@03000000/cam_sensor_suspend_front-m/soc/pinctrl@03000000/cam_sensor_active_iris.m/soc/pinctrl@03000000/cam_sensor_suspend_iris4m/soc/pinctrl@03000000/cam_sensor_active_triple_rear5n/soc/pinctrl@03000000/cam_sensor_suspend_triple_rear8n3/soc/pinctrl@03000000/cam_sensor_active_triple_rear_aux9nU/soc/pinctrl@03000000/cam_sensor_suspend_triple_rear_aux9nx/soc/pinctrl@03000000/cam_sensor_active_triple_rear_aux2:n/soc/pinctrl@03000000/cam_sensor_suspend_triple_rear_aux2"n/soc/pinctrl@03000000/cci0_active#n/soc/pinctrl@03000000/cci0_suspend"n/soc/pinctrl@03000000/cci1_active#n/soc/pinctrl@03000000/cci1_suspend"n/soc/pinctrl@03000000/cci2_active#n/soc/pinctrl@03000000/cci2_suspend"o /soc/pinctrl@03000000/cci3_active#o/soc/pinctrl@03000000/cci3_suspend+o#/soc/pinctrl@03000000/tsif0_signals_active(o8/soc/pinctrl@03000000/tsif0_sync_active+oJ/soc/pinctrl@03000000/tsif1_signals_active(o_/soc/pinctrl@03000000/tsif1_sync_active oq/soc/pinctrl@03000000/trigout_a*o{/soc/pinctrl@03000000/usb2_id_det_default$o/soc/pinctrl@03000000/emac/emac_mdc%o/soc/pinctrl@03000000/emac/emac_mdio+o/soc/pinctrl@03000000/emac/emac_rgmii_txd0+o/soc/pinctrl@03000000/emac/emac_rgmii_txd1+o/soc/pinctrl@03000000/emac/emac_rgmii_txd2+o/soc/pinctrl@03000000/emac/emac_rgmii_txd3*o/soc/pinctrl@03000000/emac/emac_rgmii_txc-o/soc/pinctrl@03000000/emac/emac_rgmii_tx_ctl+p/soc/pinctrl@03000000/emac/emac_rgmii_rxd0+p/soc/pinctrl@03000000/emac/emac_rgmii_rxd1+p#/soc/pinctrl@03000000/emac/emac_rgmii_rxd2+p3/soc/pinctrl@03000000/emac/emac_rgmii_rxd3*pC/soc/pinctrl@03000000/emac/emac_rgmii_rxc-pR/soc/pinctrl@03000000/emac/emac_rgmii_rx_ctl)pd/soc/pinctrl@03000000/emac/emac_phy_intr0pr/soc/pinctrl@03000000/emac/emac_phy_reset_state*p/soc/pinctrl@03000000/emac/emac_pin_pps_0#p/soc/pinctrl@03000000/bt_en_active,p/soc/pinctrl@03000000/conn_power_1p8_active+p/soc/pinctrl@03000000/conn_power_pa_active-p/soc/pinctrl@03000000/usb2phy_ac_en1_default-p/soc/pinctrl@03000000/usb2phy_ac_en2_default/p/soc/pinctrl@03000000/audio_ioexp_reset_activeq/soc/slpi_pinctrl@02B40000/q/soc/slpi_pinctrl@02B40000/qupv3_se20_i2c_pinsEq3/soc/slpi_pinctrl@02B40000/qupv3_se20_i2c_pins/qupv3_se20_i2c_activeDqI/soc/slpi_pinctrl@02B40000/qupv3_se20_i2c_pins/qupv3_se20_i2c_sleep/q^/soc/slpi_pinctrl@02B40000/qupv3_se21_i2c_pinsEqr/soc/slpi_pinctrl@02B40000/qupv3_se21_i2c_pins/qupv3_se21_i2c_activeDq/soc/slpi_pinctrl@02B40000/qupv3_se21_i2c_pins/qupv3_se21_i2c_sleep/q/soc/slpi_pinctrl@02B40000/qupv3_se22_i2c_pinsEq/soc/slpi_pinctrl@02B40000/qupv3_se22_i2c_pins/qupv3_se22_i2c_activeDq/soc/slpi_pinctrl@02B40000/qupv3_se22_i2c_pins/qupv3_se22_i2c_sleep/q/soc/slpi_pinctrl@02B40000/qupv3_se23_i2c_pinsEq/soc/slpi_pinctrl@02B40000/qupv3_se23_i2c_pins/qupv3_se23_i2c_activeDr/soc/slpi_pinctrl@02B40000/qupv3_se23_i2c_pins/qupv3_se23_i2c_sleep/r/soc/slpi_pinctrl@02B40000/qupv3_se21_spi_pinsEr//soc/slpi_pinctrl@02B40000/qupv3_se21_spi_pins/qupv3_se21_spi_activeDrE/soc/slpi_pinctrl@02B40000/qupv3_se21_spi_pins/qupv3_se21_spi_sleep/rZ/soc/slpi_pinctrl@02B40000/qupv3_se22_spi_pinsErn/soc/slpi_pinctrl@02B40000/qupv3_se22_spi_pins/qupv3_se22_spi_activeDr/soc/slpi_pinctrl@02B40000/qupv3_se22_spi_pins/qupv3_se22_spi_sleepr/soc/regulator-pm8150-s4r/soc/regulator-pm8150-s45r/soc/rpmh-regulator-msslvl/regulator-pm8150-s1-level5r/soc/rpmh-regulator-msslvl/regulator-pm8150-s1-level.r/soc/rpmh-regulator-smpa2/regulator-pm8150-s2.r/soc/rpmh-regulator-smpa2/regulator-pm8150-s25r/soc/rpmh-regulator-ebilvl/regulator-pm8150-s3-level5r/soc/rpmh-regulator-ebilvl/regulator-pm8150-s3-level*r/soc/rpmh-regulator-ebilvl/regulator-cdev.r/soc/rpmh-regulator-smpa5/regulator-pm8150-s5.r/soc/rpmh-regulator-smpa5/regulator-pm8150-s5.s/soc/rpmh-regulator-smpa6/regulator-pm8150-s6.s/soc/rpmh-regulator-smpa6/regulator-pm8150-s6.s/soc/rpmh-regulator-ldoa1/regulator-pm8150-l1.s/soc/rpmh-regulator-ldoa1/regulator-pm8150-l1.s/soc/rpmh-regulator-ldoa2/regulator-pm8150-l2.s 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~U/soc/ad-hoc-bus/slv-qhs-clk-ctl$~e/soc/ad-hoc-bus/slv-qhs-compute-dsp~y/soc/ad-hoc-bus/slv-qhs-cpr-cx!~/soc/ad-hoc-bus/slv-qhs-cpr-mmcx~/soc/ad-hoc-bus/slv-qhs-cpr-mx$~/soc/ad-hoc-bus/slv-qhs-crypto0-cfg"~/soc/ad-hoc-bus/slv-qhs-ddrss-cfg$~/soc/ad-hoc-bus/slv-qhs-display-cfg!~/soc/ad-hoc-bus/slv-qhs-emac-cfg~/soc/ad-hoc-bus/slv-qhs-glm"~/soc/ad-hoc-bus/slv-qhs-gpuss-cfg!/soc/ad-hoc-bus/slv-qhs-imem-cfg"/soc/ad-hoc-bus/slv-qhs-ipa!./soc/ad-hoc-bus/slv-qhs-mnoc-cfg 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