Home
last modified time | relevance | path

Searched defs:CTRL (Results 1 – 7 of 7) sorted by relevance

/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_sc000.h481 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
532 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
Dcore_cm0plus.h462 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
513 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
Dcore_cm0.h441 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
Dcore_cm3.h612 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
763 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1063 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
Dcore_sc300.h592 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
743 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1043 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
Dcore_cm4.h652 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
803 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1103 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
Dcore_cm7.h833 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
984 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1287 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member