Searched defs:Orr (Results 1 – 5 of 5) sorted by relevance
| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 1084 __ Orr(out, first, second); in GenerateDataProcInstruction() local
1198 __ Orr(temp, temp, Operand(second_lo, ShiftType::LSR, 32 - shift_value)); in GenerateLongDataProc() local
1231 __ Orr(temp, temp, Operand(second_hi, ShiftType::LSL, 32 - shift_value)); in GenerateLongDataProc() local
1604 __ Orr(out, out, temp); in GenerateEqualLong() local
1644 __ Orr(out, LowRegisterFrom(left), HighRegisterFrom(left)); in GenerateConditionLong() local
4793 __ Orr(temp1, temp1, temp2); in GenerateMinMaxFloat() local
5051 __ Orr(out_reg_hi, out_reg_hi, Operand(in_reg_lo, ShiftType::LSL, kArmBitsPerWord - rot)); in HandleLongRotate() local
5053 __ Orr(out_reg_lo, out_reg_lo, Operand(in_reg_hi, ShiftType::LSL, kArmBitsPerWord - rot)); in HandleLongRotate() local
5237 __ Orr(o_h, o_h, temp); in HandleShift() local
5256 __ Orr(o_l, o_l, temp); in HandleShift() local
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| D | code_generator_vector_arm64_sve.cc | 807 __ Orr(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecOr() local
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| D | code_generator_vector_arm64_neon.cc | 807 __ Orr(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecOr() local
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| D | intrinsics_arm_vixl.cc | 1312 __ Orr(temp3, temp3, 0xffu << 23); // uncompressed ? 0xff800000u : 0x7ff80000u in GenerateStringCompareToLoop() local
2893 __ Orr(out, temp, Operand(out, vixl32::LSL, 1)); in VisitDoubleIsInfinite() local
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| D | code_generator_arm64.cc | 2131 __ Orr(dst, lhs, rhs); in HandleBinaryOp() local
2338 __ Orr(out, left, right_operand); in VisitDataProcWithShifterOp() local
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