1 /*
2  * Copyright (C) 2016 The Android Open Source Project
3  *
4  * Licensed under the Apache License, Version 2.0 (the "License");
5  * you may not use this file except in compliance with the License.
6  * You may obtain a copy of the License at
7  *
8  *      http://www.apache.org/licenses/LICENSE-2.0
9  *
10  * Unless required by applicable law or agreed to in writing, software
11  * distributed under the License is distributed on an "AS IS" BASIS,
12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  * See the License for the specific language governing permissions and
14  * limitations under the License.
15  */
16 
17 #ifndef ART_COMPILER_DEBUG_ELF_DEBUG_FRAME_WRITER_H_
18 #define ART_COMPILER_DEBUG_ELF_DEBUG_FRAME_WRITER_H_
19 
20 #include <vector>
21 
22 #include "arch/instruction_set.h"
23 #include "debug/method_debug_info.h"
24 #include "dwarf/debug_frame_opcode_writer.h"
25 #include "dwarf/dwarf_constants.h"
26 #include "dwarf/headers.h"
27 #include "elf/elf_builder.h"
28 
29 namespace art {
30 namespace debug {
31 
32 static constexpr bool kWriteDebugFrameHdr = false;
33 
34 // Binary search table is not useful if the number of entries is small.
35 // In particular, this avoids it for the in-memory JIT mini-debug-info.
36 static constexpr size_t kMinDebugFrameHdrEntries = 100;
37 
WriteCIE(InstructionSet isa,std::vector<uint8_t> * buffer)38 static void WriteCIE(InstructionSet isa, /*inout*/ std::vector<uint8_t>* buffer) {
39   using Reg = dwarf::Reg;
40   // Scratch registers should be marked as undefined.  This tells the
41   // debugger that its value in the previous frame is not recoverable.
42   bool is64bit = Is64BitInstructionSet(isa);
43   switch (isa) {
44     case InstructionSet::kArm:
45     case InstructionSet::kThumb2: {
46       dwarf::DebugFrameOpCodeWriter<> opcodes;
47       opcodes.DefCFA(Reg::ArmCore(13), 0);  // R13(SP).
48       // core registers.
49       for (int reg = 0; reg < 13; reg++) {
50         if (reg < 4 || reg == 12) {
51           opcodes.Undefined(Reg::ArmCore(reg));
52         } else {
53           opcodes.SameValue(Reg::ArmCore(reg));
54         }
55       }
56       // fp registers.
57       for (int reg = 0; reg < 32; reg++) {
58         if (reg < 16) {
59           opcodes.Undefined(Reg::ArmFp(reg));
60         } else {
61           opcodes.SameValue(Reg::ArmFp(reg));
62         }
63       }
64       auto return_reg = Reg::ArmCore(14);  // R14(LR).
65       WriteCIE(is64bit, return_reg, opcodes, buffer);
66       return;
67     }
68     case InstructionSet::kArm64: {
69       dwarf::DebugFrameOpCodeWriter<> opcodes;
70       opcodes.DefCFA(Reg::Arm64Core(31), 0);  // R31(SP).
71       // core registers.
72       for (int reg = 0; reg < 30; reg++) {
73         if (reg < 8 || reg == 16 || reg == 17) {
74           opcodes.Undefined(Reg::Arm64Core(reg));
75         } else {
76           opcodes.SameValue(Reg::Arm64Core(reg));
77         }
78       }
79       // fp registers.
80       for (int reg = 0; reg < 32; reg++) {
81         if (reg < 8 || reg >= 16) {
82           opcodes.Undefined(Reg::Arm64Fp(reg));
83         } else {
84           opcodes.SameValue(Reg::Arm64Fp(reg));
85         }
86       }
87       auto return_reg = Reg::Arm64Core(30);  // R30(LR).
88       WriteCIE(is64bit, return_reg, opcodes, buffer);
89       return;
90     }
91     case InstructionSet::kX86: {
92       // FIXME: Add fp registers once libunwind adds support for them. Bug: 20491296
93       constexpr bool generate_opcodes_for_x86_fp = false;
94       dwarf::DebugFrameOpCodeWriter<> opcodes;
95       opcodes.DefCFA(Reg::X86Core(4), 4);   // R4(ESP).
96       opcodes.Offset(Reg::X86Core(8), -4);  // R8(EIP).
97       // core registers.
98       for (int reg = 0; reg < 8; reg++) {
99         if (reg <= 3) {
100           opcodes.Undefined(Reg::X86Core(reg));
101         } else if (reg == 4) {
102           // Stack pointer.
103         } else {
104           opcodes.SameValue(Reg::X86Core(reg));
105         }
106       }
107       // fp registers.
108       if (generate_opcodes_for_x86_fp) {
109         for (int reg = 0; reg < 8; reg++) {
110           opcodes.Undefined(Reg::X86Fp(reg));
111         }
112       }
113       auto return_reg = Reg::X86Core(8);  // R8(EIP).
114       WriteCIE(is64bit, return_reg, opcodes, buffer);
115       return;
116     }
117     case InstructionSet::kX86_64: {
118       dwarf::DebugFrameOpCodeWriter<> opcodes;
119       opcodes.DefCFA(Reg::X86_64Core(4), 8);  // R4(RSP).
120       opcodes.Offset(Reg::X86_64Core(16), -8);  // R16(RIP).
121       // core registers.
122       for (int reg = 0; reg < 16; reg++) {
123         if (reg == 4) {
124           // Stack pointer.
125         } else if (reg < 12 && reg != 3 && reg != 5) {  // except EBX and EBP.
126           opcodes.Undefined(Reg::X86_64Core(reg));
127         } else {
128           opcodes.SameValue(Reg::X86_64Core(reg));
129         }
130       }
131       // fp registers.
132       for (int reg = 0; reg < 16; reg++) {
133         if (reg < 12) {
134           opcodes.Undefined(Reg::X86_64Fp(reg));
135         } else {
136           opcodes.SameValue(Reg::X86_64Fp(reg));
137         }
138       }
139       auto return_reg = Reg::X86_64Core(16);  // R16(RIP).
140       WriteCIE(is64bit, return_reg, opcodes, buffer);
141       return;
142     }
143     case InstructionSet::kNone:
144       break;
145   }
146   LOG(FATAL) << "Cannot write CIE frame for ISA " << isa;
147   UNREACHABLE();
148 }
149 
150 template<typename ElfTypes>
WriteCFISection(ElfBuilder<ElfTypes> * builder,const ArrayRef<const MethodDebugInfo> & method_infos)151 void WriteCFISection(ElfBuilder<ElfTypes>* builder,
152                      const ArrayRef<const MethodDebugInfo>& method_infos) {
153   typedef typename ElfTypes::Addr Elf_Addr;
154 
155   // The methods can be written in any order.
156   // Let's therefore sort them in the lexicographical order of the opcodes.
157   // This has no effect on its own. However, if the final .debug_frame section is
158   // compressed it reduces the size since similar opcodes sequences are grouped.
159   std::vector<const MethodDebugInfo*> sorted_method_infos;
160   sorted_method_infos.reserve(method_infos.size());
161   for (size_t i = 0; i < method_infos.size(); i++) {
162     if (!method_infos[i].cfi.empty() && !method_infos[i].deduped) {
163       sorted_method_infos.push_back(&method_infos[i]);
164     }
165   }
166   if (sorted_method_infos.empty()) {
167     return;
168   }
169   std::stable_sort(
170       sorted_method_infos.begin(),
171       sorted_method_infos.end(),
172       [](const MethodDebugInfo* lhs, const MethodDebugInfo* rhs) {
173         ArrayRef<const uint8_t> l = lhs->cfi;
174         ArrayRef<const uint8_t> r = rhs->cfi;
175         return std::lexicographical_compare(l.begin(), l.end(), r.begin(), r.end());
176       });
177 
178   std::vector<uint32_t> binary_search_table;
179   if (kWriteDebugFrameHdr) {
180     binary_search_table.reserve(2 * sorted_method_infos.size());
181   }
182 
183   // Write .debug_frame section.
184   auto* cfi_section = builder->GetDebugFrame();
185   {
186     cfi_section->Start();
187     const bool is64bit = Is64BitInstructionSet(builder->GetIsa());
188     std::vector<uint8_t> buffer;  // Small temporary buffer.
189     WriteCIE(builder->GetIsa(), &buffer);
190     cfi_section->WriteFully(buffer.data(), buffer.size());
191     buffer.clear();
192     for (const MethodDebugInfo* mi : sorted_method_infos) {
193       DCHECK(!mi->deduped);
194       DCHECK(!mi->cfi.empty());
195       const Elf_Addr code_address = mi->code_address +
196           (mi->is_code_address_text_relative ? builder->GetText()->GetAddress() : 0);
197       if (kWriteDebugFrameHdr) {
198         binary_search_table.push_back(dchecked_integral_cast<uint32_t>(code_address));
199         binary_search_table.push_back(cfi_section->GetPosition());
200       }
201       dwarf::WriteFDE(is64bit,
202                       /* cie_pointer= */ 0,
203                       code_address,
204                       mi->code_size,
205                       mi->cfi,
206                       &buffer);
207       cfi_section->WriteFully(buffer.data(), buffer.size());
208       buffer.clear();
209     }
210     cfi_section->End();
211   }
212 
213   if (kWriteDebugFrameHdr && method_infos.size() > kMinDebugFrameHdrEntries) {
214     std::sort(binary_search_table.begin(), binary_search_table.end());
215 
216     // Custom Android section. It is very similar to the official .eh_frame_hdr format.
217     std::vector<uint8_t> header_buffer;
218     dwarf::Writer<> header(&header_buffer);
219     header.PushUint8(1);  // Version.
220     header.PushUint8(dwarf::DW_EH_PE_omit);    // Encoding of .eh_frame pointer - none.
221     header.PushUint8(dwarf::DW_EH_PE_udata4);  // Encoding of binary search table size.
222     header.PushUint8(dwarf::DW_EH_PE_udata4);  // Encoding of binary search table data.
223     header.PushUint32(dchecked_integral_cast<uint32_t>(binary_search_table.size()/2));
224 
225     auto* header_section = builder->GetDebugFrameHdr();
226     header_section->Start();
227     header_section->WriteFully(header_buffer.data(), header_buffer.size());
228     header_section->WriteFully(binary_search_table.data(), binary_search_table.size());
229     header_section->End();
230   }
231 }
232 
233 }  // namespace debug
234 }  // namespace art
235 
236 #endif  // ART_COMPILER_DEBUG_ELF_DEBUG_FRAME_WRITER_H_
237 
238