1 /******************************************************************************* 2 * Copyright (C) 2018 Cadence Design Systems, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining 5 * a copy of this software and associated documentation files (the 6 * "Software"), to use this Software with Cadence processor cores only and 7 * not with any other processors and platforms, subject to 8 * the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included 11 * in all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 15 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 16 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 17 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 18 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 19 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 21 ******************************************************************************/ 22 23 24 #ifndef __DSP_COMM_H__ 25 #define __DSP_COMM_H__ 26 27 #include <xtensa/config/core.h> 28 #include <xtensa/simcall.h> 29 30 #define DSP_FLUSH_PIECE_CACHE(addr, size) xthal_dcache_region_writeback(addr, size) 31 #define DSP_FLUSH_ALL_CACHE() xthal_dcache_all_writeback() 32 #define DSP_INVALIDATE_PIECE_CACHE(addr, size) xthal_dcache_region_invalidate(addr, size) 33 #define DSP_INVALIDATE_ALL_CACHE() xthal_dcache_all_invalidate() 34 35 #define memset(d,uCData,size) dsp_memset(d,uCData,size) 36 #define memcpy(d,s,size) dsp_memcpy(d,s,size) 37 #define divsi3(a,b) division(a,b) 38 #define _divsi3(a,b) division(a,b) 39 40 void dsp_memcpy(void *d, void *s, unsigned int size); 41 void dsp_memset(void *d, unsigned char ucData, unsigned int size); 42 int division(int a, int b); 43 44 #endif /* end of dsp_comm.h */ 45 46