1/*
2 * Copyright (C) 2013 The Android Open Source Project
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *  * Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 *  * Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in
12 *    the documentation and/or other materials provided with the
13 *    distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
18 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
19 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
21 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
22 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
23 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
25 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28/*
29 * Copyright (c) 2013 ARM Ltd
30 * All rights reserved.
31 *
32 * Redistribution and use in source and binary forms, with or without
33 * modification, are permitted provided that the following conditions
34 * are met:
35 * 1. Redistributions of source code must retain the above copyright
36 *    notice, this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright
38 *    notice, this list of conditions and the following disclaimer in the
39 *    documentation and/or other materials provided with the distribution.
40 * 3. The name of the company may not be used to endorse or promote
41 *    products derived from this software without specific prior written
42 *    permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
45 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
46 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
49 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
50 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
51 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
52 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
53 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55
56#include <private/bionic_asm.h>
57
58    .syntax unified
59
60    // To avoid warning about deprecated instructions, add an explicit
61    // arch. The code generated is exactly the same.
62    .arch armv7-a
63
64    .thumb
65    .thumb_func
66
67ENTRY(strlen_a9)
68    pld     [r0, #0]
69    mov     r1, r0
70
71    ands    r3, r0, #7
72    bne     align_src
73
74    .p2align 2
75mainloop:
76    ldmia   r1!, {r2, r3}
77
78    pld     [r1, #64]
79
80    sub     ip, r2, #0x01010101
81    bic     ip, ip, r2
82    ands    ip, ip, #0x80808080
83    bne     zero_in_first_register
84
85    sub     ip, r3, #0x01010101
86    bic     ip, ip, r3
87    ands    ip, ip, #0x80808080
88    bne     zero_in_second_register
89    b       mainloop
90
91zero_in_first_register:
92    sub     r0, r1, r0
93    // Check for zero in byte 0.
94    lsls    r2, ip, #17
95    beq     check_byte1_reg1
96
97    sub     r0, r0, #8
98    bx      lr
99
100check_byte1_reg1:
101    bcc     check_byte2_reg1
102
103    sub     r0, r0, #7
104    bx      lr
105
106check_byte2_reg1:
107    // Check for zero in byte 2.
108    tst     ip, #0x800000
109    itt     ne
110    subne   r0, r0, #6
111    bxne    lr
112    sub     r0, r0, #5
113    bx      lr
114
115zero_in_second_register:
116    sub     r0, r1, r0
117    // Check for zero in byte 0.
118    lsls    r2, ip, #17
119    beq     check_byte1_reg2
120
121    sub     r0, r0, #4
122    bx      lr
123
124check_byte1_reg2:
125    bcc     check_byte2_reg2
126
127    sub     r0, r0, #3
128    bx      lr
129
130check_byte2_reg2:
131    // Check for zero in byte 2.
132    tst     ip, #0x800000
133    itt     ne
134    subne   r0, r0, #2
135    bxne    lr
136    sub     r0, r0, #1
137    bx      lr
138
139align_src:
140    // Align to a double word (64 bits).
141    rsb     r3, r3, #8
142    lsls    ip, r3, #31
143    beq     align_to_32
144
145    ldrb    r2, [r1], #1
146    cbz     r2, done
147
148align_to_32:
149    bcc     align_to_64
150
151    ldrb    r2, [r1], #1
152    cbz     r2, done
153    ldrb    r2, [r1], #1
154    cbz     r2, done
155
156align_to_64:
157    tst     r3, #4
158    beq     mainloop
159    ldr     r2, [r1], #4
160
161    sub     ip, r2, #0x01010101
162    bic     ip, ip, r2
163    ands    ip, ip, #0x80808080
164    bne     zero_in_second_register
165    b       mainloop
166
167done:
168    sub     r0, r1, r0
169    sub     r0, r0, #1
170    bx      lr
171END(strlen_a9)
172