1/*
2 * Copyright (C) 2010 The Android Open Source Project
3 * Copyright (c) 2008 ARM Ltd
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 * 3. The name of the company may not be used to endorse or promote
15 *    products derived from this software without specific prior written
16 *    permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21 * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
23 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
24 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
25 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
26 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
27 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Android adaptation and tweak by Jim Huang <jserv@0xlab.org>.
30 */
31
32#include <private/bionic_asm.h>
33
34.syntax unified
35
36// To avoid warning about deprecated instructions, add an explicit
37// arch. The code generated is exactly the same.
38.arch armv7-a
39
40ENTRY(strcpy_generic)
41	pld	[r1, #0]
42	eor	r2, r0, r1
43	mov	ip, r0
44	tst	r2, #3
45	bne	4f
46	tst	r1, #3
47	bne	3f
485:
49	str	r5, [sp, #-4]!
50	mov	r5, #0x01
51	orr	r5, r5, r5, lsl #8
52	orr	r5, r5, r5, lsl #16
53
54	str	r4, [sp, #-4]!
55	tst	r1, #4
56	ldr	r3, [r1], #4
57	beq	2f
58	sub	r2, r3, r5
59	bics	r2, r2, r3
60	tst	r2, r5, lsl #7
61	itt	eq
62	streq	r3, [ip], #4
63	ldreq	r3, [r1], #4
64	bne	1f
65       /* Inner loop.  We now know that r1 is 64-bit aligned, so we
66	  can safely fetch up to two words.  This allows us to avoid
67	  load stalls.  */
68	.p2align 2
692:
70	pld	[r1, #8]
71	ldr	r4, [r1], #4
72	sub	r2, r3, r5
73	bics	r2, r2, r3
74	tst	r2, r5, lsl #7
75	sub	r2, r4, r5
76	bne	1f
77	str	r3, [ip], #4
78	bics	r2, r2, r4
79	tst	r2, r5, lsl #7
80	itt	eq
81	ldreq	r3, [r1], #4
82	streq	r4, [ip], #4
83	beq	2b
84	mov	r3, r4
851:
86#ifdef __ARMEB__
87	rors	r3, r3, #24
88#endif
89	strb	r3, [ip], #1
90	tst	r3, #0xff
91#ifdef __ARMEL__
92	ror	r3, r3, #8
93#endif
94	bne	1b
95	ldr	r4, [sp], #4
96	ldr	r5, [sp], #4
97	bx	lr
98
99       /* Strings have the same offset from word alignment, but it's
100	  not zero.  */
1013:
102	tst	r1, #1
103	beq	1f
104	ldrb	r2, [r1], #1
105	strb	r2, [ip], #1
106	cmp	r2, #0
107	it	eq
108	bxeq	lr
1091:
110	tst	r1, #2
111	beq	5b
112	ldrh	r2, [r1], #2
113#ifdef __ARMEB__
114	tst	r2, #0xff00
115	iteet	ne
116	strhne	r2, [ip], #2
117	lsreq	r2, r2, #8
118	strbeq	r2, [ip]
119	tstne	r2, #0xff
120#else
121	tst	r2, #0xff
122	itet	ne
123	strhne	r2, [ip], #2
124	strbeq	r2, [ip]
125	tstne	r2, #0xff00
126#endif
127	bne	5b
128	bx	lr
129
130       /* src and dst do not have a common word-alignement.  Fall back to
131	  byte copying.  */
1324:
133	ldrb	r2, [r1], #1
134	strb	r2, [ip], #1
135	cmp	r2, #0
136	bne	4b
137	bx	lr
138END(strcpy_generic)
139