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Searched refs:R4 (Results 1 – 7 of 7) sorted by relevance

/art/compiler/utils/
Dassembler_thumb_test.cc119 const ManagedRegister hidden_arg_register = ArmManagedRegister::FromCoreRegister(R4); in TEST_F()
199 #define R4 vixl::aarch32::r4 macro
205 __ LoadFromOffset(kLoadWord, R2, R4, 12); in TEST_F()
206 __ LoadFromOffset(kLoadWord, R2, R4, 0xfff); in TEST_F()
207 __ LoadFromOffset(kLoadWord, R2, R4, 0x1000); in TEST_F()
208 __ LoadFromOffset(kLoadWord, R2, R4, 0x1000a4); in TEST_F()
209 __ LoadFromOffset(kLoadWord, R2, R4, 0x101000); in TEST_F()
210 __ LoadFromOffset(kLoadWord, R4, R4, 0x101000); in TEST_F()
211 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 12); in TEST_F()
212 __ LoadFromOffset(kLoadUnsignedHalfword, R2, R4, 0xfff); in TEST_F()
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/art/runtime/arch/arm/
Dregisters_arm.h31 R4 = 4, enumerator
Dcallee_save_frame_arm.h39 (1 << art::arm::R4) | (1 << art::arm::R9);
42 (1 << art::arm::R4) | (1 << art::arm::R9) | (1 << art::arm::R12);
/art/compiler/jni/quick/arm/
Dcalling_convention_arm.cc128 ArmManagedRegister::FromCoreRegister(R4),
529 return callee_save.Equals(ArmManagedRegister::FromCoreRegister(R4)); in HiddenArgumentRegister()
533 [](Register reg) { return reg == R4; })); in HiddenArgumentRegister()
534 return ArmManagedRegister::FromCoreRegister(R4); in HiddenArgumentRegister()
/art/compiler/optimizing/
Dcodegen_test_utils.h96 blocked_core_registers_[arm::R4] = true; in SetupBlockedRegisters()
Dcode_generator_arm_vixl.cc2178 if (!blocked_core_registers_[R4]) { in GenerateFrameEntry()
2489 return Location::RegisterLocation(R4); in GetMethodLocation()
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc271 EXPECT_EQ(R4, reg.AsRegisterPairLow()); in TEST()
273 EXPECT_TRUE(reg.Equals(ArmManagedRegister::FromCoreRegisterPair(R4))); in TEST()