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Searched refs:arm (Results 1 – 25 of 68) sorted by relevance

123

/art/runtime/arch/arm/
Dcallee_save_frame_arm.h29 namespace arm {
32 (1 << art::arm::LR);
34 (1 << art::arm::R5) | (1 << art::arm::R6) | (1 << art::arm::R7) | (1 << art::arm::R8) |
35 (1 << art::arm::R10) | (1 << art::arm::R11);
37 (1 << art::arm::R1) | (1 << art::arm::R2) | (1 << art::arm::R3);
39 (1 << art::arm::R4) | (1 << art::arm::R9);
41 (1 << art::arm::R0) | (1 << art::arm::R1) | (1 << art::arm::R2) | (1 << art::arm::R3) |
42 (1 << art::arm::R4) | (1 << art::arm::R9) | (1 << art::arm::R12);
47 (1 << art::arm::S0) | (1 << art::arm::S1) | (1 << art::arm::S2) | (1 << art::arm::S3) |
48 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
[all …]
Dregisters_arm.cc22 namespace arm { namespace
Dregisters_arm.h23 namespace arm {
Djni_frame_arm.h28 namespace arm {
/art/compiler/optimizing/
Dcodegen_test_utils.h86 class TestCodeGeneratorARMVIXL : public arm::CodeGeneratorARMVIXL {
89 : arm::CodeGeneratorARMVIXL(graph, compiler_options) { in TestCodeGeneratorARMVIXL()
90 AddAllocatedRegister(Location::RegisterLocation(arm::R6)); in TestCodeGeneratorARMVIXL()
91 AddAllocatedRegister(Location::RegisterLocation(arm::R7)); in TestCodeGeneratorARMVIXL()
95 arm::CodeGeneratorARMVIXL::SetupBlockedRegisters(); in SetupBlockedRegisters()
96 blocked_core_registers_[arm::R4] = true; in SetupBlockedRegisters()
97 blocked_core_registers_[arm::R6] = false; in SetupBlockedRegisters()
98 blocked_core_registers_[arm::R7] = false; in SetupBlockedRegisters()
Dinstruction_simplifier_arm.h24 namespace arm {
/art/compiler/utils/
Dmanaged_register.h27 namespace arm {
51 constexpr arm::ArmManagedRegister AsArm() const;
/art/compiler/
DAndroid.bp101 arm: {
103 "jni/quick/arm/calling_convention_arm.cc",
111 "utils/arm/assembler_arm_vixl.cc",
112 "utils/arm/constants_arm.cc",
113 "utils/arm/jni_macro_assembler_arm_vixl.cc",
114 "utils/arm/managed_register_arm.cc",
189 "utils/arm/constants_arm.h",
201 arm: {
282 arm: {
423 arm: {
[all …]
/art/test/655-checker-simd-arm-opt/
Dinfo.txt1 Checker test for arm and arm64 simd optimizations.
DAndroid.bp3 name: "art-run-test-655-checker-simd-arm-opt",
/art/test/527-checker-array-access-split/
Dinfo.txt1 Test arm- and arm64-specific array access optimization.
/art/test/527-checker-array-access-simd/
Dinfo.txt1 Test arm- and arm64-specific array access optimization for simd loops.
/art/test/558-switch/
Dinfo.txt2 code for arm.
/art/test/434-shifter-operand/
Dinfo.txt1 Regression test for the arm backend of the optimizing
/art/compiler/utils/arm/
Dconstants_arm.cc20 namespace arm { namespace
Dassembler_arm_shared.h21 namespace arm {
Dmanaged_register_arm.h26 namespace arm {
267 constexpr inline arm::ArmManagedRegister ManagedRegister::AsArm() const { in AsArm()
268 arm::ArmManagedRegister reg(id_); in AsArm()
Dconstants_arm.h31 namespace arm {
/art/test/668-aiobe/
Dinfo.txt1 Regression test for the mterp arm interpreter which used to throw
/art/runtime/
DAndroid.bp18 // we use gold as the linker (arm, x86, x86_64). The symbol is used by the debuggers to detect when
31 arm: {
260 "arch/arm/instruction_set_features_arm.cc",
261 "arch/arm/registers_arm.cc",
287 arm: {
291 ":libart_mterp.arm",
292 "arch/arm/context_arm.cc",
293 "arch/arm/entrypoints_init_arm.cc",
294 "arch/arm/instruction_set_features_assembly_tests.S",
295 "arch/arm/jni_entrypoints_arm.S",
[all …]
/art/runtime/arch/
Dcontext-inl.h27 #define RUNTIME_CONTEXT_TYPE arm::ArmContext
Darch_test.cc44 namespace arm { namespace
142 TEST_ARCH(Arm, arm)
/art/tools/golem/
Dbuild-target.sh249 if [[ $target_product = arm* ]]; then
294 if [[ $config == linux-arm* ]]; then
344 if [[ $config == *-arm* ]]; then
/art/disassembler/
Ddisassembler_arm.h27 namespace arm {
Ddisassembler.cc50 return new arm::DisassemblerArm(options); in Create()

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