| /art/compiler/jni/quick/ |
| D | jni_compiler.cc | 60 ManagedRegister in_reg);
293 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in ArtJniCompileMethodInternal() local
294 __ VerifyObject(in_reg, mr_conv->IsCurrentArgPossiblyNull()); in ArtJniCompileMethodInternal()
295 __ StoreRef(handle_scope_offset, in_reg); in ArtJniCompileMethodInternal()
719 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in CopyParameter() local
722 __ CreateHandleScopeEntry(out_reg, handle_scope_offset, in_reg, null_allowed); in CopyParameter()
726 __ Move(out_reg, in_reg, mr_conv->CurrentParamSize()); in CopyParameter()
758 ManagedRegister in_reg = mr_conv->CurrentParamRegister(); in CopyParameter() local
770 __ Store(out_off, in_reg, param_size); in CopyParameter()
775 __ StoreSpanning(out_off, in_reg, in_off); in CopyParameter()
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| /art/compiler/utils/x86_64/ |
| D | jni_macro_assembler_x86_64.cc | 549 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); in CreateHandleScopeEntry() local
550 if (in_reg.IsNoRegister()) { // TODO(64): && null_allowed in CreateHandleScopeEntry()
552 in_reg = out_reg; in CreateHandleScopeEntry()
554 __ movl(in_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset)); in CreateHandleScopeEntry()
556 CHECK(in_reg.IsCpuRegister()); in CreateHandleScopeEntry()
558 VerifyObject(in_reg, null_allowed); in CreateHandleScopeEntry()
561 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
564 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in CreateHandleScopeEntry()
594 X86_64ManagedRegister in_reg = min_reg.AsX86_64(); in LoadReferenceFromHandleScope() local
596 CHECK(in_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_x86_64.h | 155 ManagedRegister in_reg,
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| /art/compiler/utils/x86/ |
| D | jni_macro_assembler_x86.cc | 464 X86ManagedRegister in_reg = min_reg.AsX86(); in CreateHandleScopeEntry() local
465 CHECK(in_reg.IsCpuRegister()); in CreateHandleScopeEntry()
467 VerifyObject(in_reg, null_allowed); in CreateHandleScopeEntry()
470 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
473 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in CreateHandleScopeEntry()
503 X86ManagedRegister in_reg = min_reg.AsX86(); in LoadReferenceFromHandleScope() local
505 CHECK(in_reg.IsCpuRegister()); in LoadReferenceFromHandleScope()
507 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
510 __ testl(in_reg.AsCpuRegister(), in_reg.AsCpuRegister()); in LoadReferenceFromHandleScope()
512 __ movl(out_reg.AsCpuRegister(), Address(in_reg.AsCpuRegister(), 0)); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_x86.h | 135 ManagedRegister in_reg,
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| /art/compiler/utils/arm64/ |
| D | jni_macro_assembler_arm64.cc | 658 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); in CreateHandleScopeEntry() local
660 CHECK(in_reg.IsNoRegister() || in_reg.IsXRegister()) << in_reg; in CreateHandleScopeEntry()
666 if (in_reg.IsNoRegister()) { in CreateHandleScopeEntry()
669 in_reg = out_reg; in CreateHandleScopeEntry()
671 ___ Cmp(reg_w(in_reg.AsOverlappingWRegister()), 0); in CreateHandleScopeEntry()
672 if (!out_reg.Equals(in_reg)) { in CreateHandleScopeEntry()
704 Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); in LoadReferenceFromHandleScope() local
706 CHECK(in_reg.IsXRegister()) << in_reg; in LoadReferenceFromHandleScope()
708 if (!out_reg.Equals(in_reg)) { in LoadReferenceFromHandleScope()
712 ___ Cbz(reg_x(in_reg.AsXRegister()), &exit); in LoadReferenceFromHandleScope()
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| D | jni_macro_assembler_arm64.h | 144 ManagedRegister in_reg,
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| /art/compiler/utils/arm/ |
| D | jni_macro_assembler_arm_vixl.cc | 801 vixl::aarch32::Register in_reg = in CreateHandleScopeEntry() local
809 if (!in_reg.IsValid()) { in CreateHandleScopeEntry()
811 in_reg = out_reg; in CreateHandleScopeEntry()
814 temps.Exclude(in_reg); in CreateHandleScopeEntry()
815 ___ Cmp(in_reg, 0); in CreateHandleScopeEntry()
818 if (!out_reg.Is(in_reg)) { in CreateHandleScopeEntry()
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| D | jni_macro_assembler_arm_vixl.h | 162 ManagedRegister in_reg,
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| /art/tools/dexanalyze/ |
| D | dexanalyze_bytecode.cc | 439 uint32_t in_reg = inst->VRegB_22c(); in ProcessCodeItem() local
445 ExtendPrefix(&in_reg, &local_type); in ProcessCodeItem()
446 CHECK(InstNibbles(new_opcode, {in_reg, out_reg, local_type})); in ProcessCodeItem()
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| /art/compiler/utils/ |
| D | jni_macro_assembler.h | 217 ManagedRegister in_reg,
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| /art/compiler/optimizing/ |
| D | intrinsics_arm_vixl.cc | 416 vixl32::SRegister in_reg = InputSRegisterAt(invoke, 0); in VisitMathRoundFloat() local
424 __ Vcvta(S32, F32, temp1, in_reg); in VisitMathRoundFloat()
434 __ Vrinta(F32, temp1, in_reg); in VisitMathRoundFloat()
436 __ Vsub(F32, temp1, in_reg, temp1); in VisitMathRoundFloat()
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| D | intrinsics_arm64.cc | 528 VRegister in_reg = is_double ? DRegisterFrom(l->InAt(0)) : SRegisterFrom(l->InAt(0)); in GenMathRound() local
534 __ Fcvtas(out_reg, in_reg); in GenMathRound()
542 __ Frinta(tmp_fp, in_reg); in GenMathRound()
543 __ Fsub(tmp_fp, in_reg, tmp_fp); in GenMathRound()
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| D | code_generator_arm64.cc | 5766 Register in_reg = InputRegisterAt(abs, 0); in VisitAbs() local
5768 __ Cmp(in_reg, Operand(0)); in VisitAbs()
5769 __ Cneg(out_reg, in_reg, lt); in VisitAbs()
5774 VRegister in_reg = InputFPRegisterAt(abs, 0); in VisitAbs() local
5776 __ Fabs(out_reg, in_reg); in VisitAbs()
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| D | code_generator_arm_vixl.cc | 4920 vixl32::Register in_reg = RegisterFrom(locations->InAt(0)); in VisitAbs() local
4923 __ Asr(mask, in_reg, 31); in VisitAbs()
4924 __ Add(out_reg, in_reg, mask); in VisitAbs()
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