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Searched refs:lr (Results 1 – 25 of 28) sorted by relevance

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/art/runtime/arch/arm/
Dmemcmp16_arm.S39 bxeq lr
61 bxne lr
64 bx lr
68 0: push {r4, lr}
71 .cfi_rel_offset lr, 4
82 popne {r4, lr}
83 bxne lr
109 ldr lr, [r1, #4]!
113 eorseq r0, r0, lr
115 ldreq lr, [r1, #4]!
[all …]
Djni_entrypoints_arm.S25 push {r0, r1, r2, r3, lr} @ spill regs
27 .cfi_rel_offset lr, 16
50 pop {r0, r1, r2, r3, lr} @ restore regs
52 .cfi_restore lr
84 ldr lr, [sp, #20]
90 ldrd ip, lr, [r4, #FRAME_SIZE_SAVE_REFS_AND_ARGS]
92 strd ip, lr, [r4], #8
106 stmia ip, {r1-r3, r5-r8, r10-r11, lr} // LR: Save return address for tail call from JNI stub.
120 pop {r1, lr}
122 .cfi_restore lr
[all …]
Dquick_entrypoints_arm.S35 push {r5-r8, r10-r11, lr} @ 7 words of callee saves
43 .cfi_rel_offset lr, 24
64 pop {r5-r8, r10-r11, lr} @ 7 words of callee saves
71 .cfi_restore lr
118 push {r0-r12, lr} @ 14 words of callee saves and args.
133 .cfi_rel_offset lr, 52
142 pop {r0-r12, lr} @ 14 words of callee saves
156 .cfi_restore lr
524 str lr, [sp, r10] @ Store link register per the compiler ABI
543 ldr lr, [sp, #56] @ Load LR from gprs_, 56 = 4 * 14.
[all …]
Dinstruction_set_features_assembly_tests.S41 bx lr
64 bx lr
Dasm_support_arm.S192 push {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
203 .cfi_rel_offset lr, 36
222 pop {r1-r3, r5-r8, r10-r11, lr} @ 10 words of callee saves and args.
232 .cfi_restore lr
240 push {r4-r11, lr} @ 9 words (36 bytes) of callee saves.
250 .cfi_rel_offset lr, 32
/art/runtime/interpreter/mterp/arm/
Dcontrol_flow.S147 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
149 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
162 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
164 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
171 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
173 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
186 ldr lr, [rSELF, #THREAD_FLAGS_OFFSET]
188 ands lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
Dfloating_point.S22 SET_VREG_FLOAT s2, r9, lr @ vAA<- s2
352 bx lr @ return
392 bx lr @ return
Darithmetic.S166 CLEAR_SHADOW_PAIR rINST, lr, ip @ Zero out the shadow regs
201 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
269 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
292 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero shadow regs
547 umull r1, lr, r2, r0 @ r1/lr <- ZxX
550 add r2, r2, lr @ r2<- lr + low(ZxW + (YxX))
551 CLEAR_SHADOW_PAIR r0, lr, ip @ Zero out the shadow regs
575 umull r1, lr, r2, r0 @ r1/lr <- ZxX
579 add r2, r2, lr @ r2<- r2 + low(ZxW + (YxX))
785 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
[all …]
Dother.S116 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
129 CLEAR_SHADOW_PAIR r3, r2, lr @ Zero out the shadow regs
280 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
294 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
306 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA]
310 SET_VREG_WIDE_BY_ADDR r0, r1, lr @ fp[AAAA]<- r0/r1
322 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs
Dmain.S385 stmfd sp!, {r3-r10,fp,lr} @ save 10 regs, (r3 just to align 64)
396 .cfi_rel_offset lr, 36
Dobject.S161 CLEAR_SHADOW_PAIR r2, ip, lr @ Zero out the shadow regs
Darray.S86 CLEAR_SHADOW_PAIR r9, lr, ip @ Zero out the shadow regs
/art/runtime/arch/arm64/
Djni_entrypoints_arm64.S110 stp x15, lr, [sp, #128]
111 .cfi_rel_offset lr, 136
115 mov x1, lr // x1 := caller_pc
129 ldp x15, lr, [sp, #128]
130 .cfi_restore lr
145 mov xIP1, lr
194 str lr, [x29, #__SIZEOF_POINTER__]
203 str lr, [x29, #(FRAME_SIZE_SAVE_REFS_AND_ARGS - __SIZEOF_POINTER__)]
232 RESTORE_REG_BASE x29, lr, __SIZEOF_POINTER__
319 str lr, [x29, #__SIZEOF_POINTER__]
Dquick_entrypoints_arm64.S280 .cfi_rel_offset lr, 0
285 mov x0, lr // pass the fault address stored in LR by the fault handler.
805 str lr, [sp, x1]
2032 br lr
2405 br lr // Do not use RET as we do not enter the entrypoint with "BL".
2468 ldr x0, [lr, #\ldr_offset] // Load the instruction.
2543 ldr wIP1, [lr, #BAKER_MARK_INTROSPECTION_FIELD_LDR_OFFSET] // Load the instruction.
/art/runtime/interpreter/mterp/arm64/
Dmain.S408 SAVE_TWO_REGS fp, lr, 64
607 ldr lr, [xSELF, #THREAD_FLAGS_OFFSET]
611 ands lr, lr, #THREAD_SUSPEND_OR_CHECKPOINT_REQUEST
749 RESTORE_TWO_REGS fp, lr, 64
767 RESTORE_TWO_REGS fp, lr, 64
/art/compiler/utils/arm64/
Djni_macro_assembler_arm64.cc638 ___ Ldr(lr, MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); in Call()
639 ___ Blr(lr); in Call()
644 ___ Ldr(lr, MEM_OP(reg_x(SP), base.Int32Value())); in Call()
645 ___ Ldr(lr, MEM_OP(lr, offs.Int32Value())); in Call()
646 ___ Blr(lr); in Call()
772 ___ Ldr(lr, in EmitExceptionPoll()
776 ___ Blr(lr); in EmitExceptionPoll()
/art/compiler/utils/
Dassembler_thumb_test_expected.cc.inc2 " 0: 2d e9 e0 4d push.w {r5, r6, r7, r8, r10, r11, lr}\n"
44 " 8a: d0 f8 30 e0 ldr.w lr, [r0, #48]\n"
45 " 8e: f0 47 blx lr\n"
152 " 218: bd e8 e0 4d pop.w {r5, r6, r7, r8, r10, r11, lr}\n"
154 " 220: 70 47 bx lr\n"
156 " 224: d9 f8 e0 e2 ldr.w lr, [r9, #736]\n"
157 " 228: f0 47 blx lr\n"
/art/compiler/optimizing/
Doptimizing_cfi_test_expected.inc11 // 0x00000000: push {r5, r6, lr}
47 // 0x00000008: stp x22, lr, [sp, #48]
59 // 0x00000018: ldp x22, lr, [sp, #48]
163 // 0x00000000: push {r5, r6, lr}
Dcode_generator_arm64.cc957 AddAllocatedRegister(LocationFrom(lr)); in CodeGeneratorARM64()
1163 __ Stp(kArtMethodRegister, lr, MemOperand(sp, 0)); in MaybeIncrementHotness()
1172 __ Ldr(lr, MemOperand(tr, entrypoint_offset)); in MaybeIncrementHotness()
1175 __ Blr(lr); in MaybeIncrementHotness()
1178 __ Ldr(lr, MemOperand(sp, 8)); in MaybeIncrementHotness()
1830 __ Ldr(lr, MemOperand(tr, entrypoint_offset.Int32Value())); in InvokeRuntime()
1833 __ blr(lr); in InvokeRuntime()
1851 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in InvokeRuntimeWithoutRecordingPcInfo()
1852 __ Blr(lr); in InvokeRuntimeWithoutRecordingPcInfo()
4356 __ Ldr(lr, MemOperand(temp, entry_point.Int32Value())); in VisitInvokeInterface()
[all …]
Dcode_generator_arm_vixl.cc2135 (1 << lr.GetCode()) | (1 << r0.GetCode()) | (1 << r1.GetCode()) | (1 << r2.GetCode()); in MaybeIncrementHotness()
2138 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in MaybeIncrementHotness()
2139 __ Blx(lr); in MaybeIncrementHotness()
2148 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in MaybeIncrementHotness()
2149 __ Blx(lr); in MaybeIncrementHotness()
2271 __ Bx(lr); in GenerateFrameExit()
2569 __ Ldr(lr, MemOperand(tr, entrypoint_offset.Int32Value())); in InvokeRuntime()
2575 __ blx(lr); in InvokeRuntime()
2595 __ Ldr(lr, MemOperand(tr, entry_point_offset)); in InvokeRuntimeWithoutRecordingPcInfo()
2596 __ Blx(lr); in InvokeRuntimeWithoutRecordingPcInfo()
[all …]
Dcode_generator_arm64.h96 vixl::aarch64::lr);
944 DCHECK(reg < vixl::aarch64::lr.GetCode() && in CheckValidReg()
/art/compiler/utils/arm/
Djni_macro_assembler_arm_vixl.cc196 ___ Bx(vixl32::lr); in RemoveFrame()
895 asm_.LoadFromOffset(kLoadWord, lr, base, offset.Int32Value()); in Call()
896 ___ Blx(lr); in Call()
902 asm_.LoadFromOffset(kLoadWord, lr, sp, base.Int32Value()); in Call()
903 asm_.LoadFromOffset(kLoadWord, lr, lr, offset.Int32Value()); in Call()
904 ___ Blx(lr); in Call()
986 ___ Ldr(lr, in EmitExceptionPoll()
989 ___ Blx(lr); in EmitExceptionPoll()
/art/compiler/jni/
Djni_cfi_test_expected.inc21 // 0x00000000: push {r5,r6,r7,r8,r10,r11,lr}
80 // 0x00000020: pop {r5,r6,r7,r8,r10,r11,lr}
82 // 0x00000028: bx lr
128 // 0x00000018: stp x29, lr, [sp, #176]
168 // 0x0000005c: ldp x29, lr, [sp, #176]
/art/runtime/interpreter/mterp/arm64ng/
Dmain.S428 RESTORE_TWO_REGS x29, lr, 144
860 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
861 blr lr
1109 ldr lr, [x0, #ART_METHOD_QUICK_CODE_OFFSET_64]
1110 blr lr
1640 ldr lr, [xSELF, #THREAD_ALLOC_OBJECT_ENTRYPOINT_OFFSET]
1641 blr lr
1667 ldr lr, [xSELF, #THREAD_ALLOC_ARRAY_ENTRYPOINT_OFFSET]
1668 blr lr
2011 SAVE_TWO_REGS x29, lr, 128
/art/runtime/
Dinstrumentation.cc1390 uintptr_t lr, in PushInstrumentationStackFrame() argument
1397 << reinterpret_cast<void*>(lr); in PushInstrumentationStackFrame()
1417 h_this.Get(), method, lr, frame_id, interpreter_entry, current_force_deopt_id_); in PushInstrumentationStackFrame()

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