1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ***   To edit the content of this header, modify the corresponding
11  ***   source file (e.g. under external/kernel-headers/original/) then
12  ***   run bionic/libc/kernel/tools/update_all.py
13  ***
14  ***   Any manual change here will be lost the next time this script will
15  ***   be run. You've been warned!
16  ***
17  ****************************************************************************
18  ****************************************************************************/
19 #ifndef __AMDGPU_DRM_H__
20 #define __AMDGPU_DRM_H__
21 #include "drm.h"
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 #define DRM_AMDGPU_GEM_CREATE 0x00
26 #define DRM_AMDGPU_GEM_MMAP 0x01
27 #define DRM_AMDGPU_CTX 0x02
28 #define DRM_AMDGPU_BO_LIST 0x03
29 #define DRM_AMDGPU_CS 0x04
30 #define DRM_AMDGPU_INFO 0x05
31 #define DRM_AMDGPU_GEM_METADATA 0x06
32 #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07
33 #define DRM_AMDGPU_GEM_VA 0x08
34 #define DRM_AMDGPU_WAIT_CS 0x09
35 #define DRM_AMDGPU_GEM_OP 0x10
36 #define DRM_AMDGPU_GEM_USERPTR 0x11
37 #define DRM_AMDGPU_WAIT_FENCES 0x12
38 #define DRM_AMDGPU_VM 0x13
39 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
40 #define DRM_AMDGPU_SCHED 0x15
41 #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
42 #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
43 #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx)
44 #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list)
45 #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs)
46 #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info)
47 #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata)
48 #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle)
49 #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va)
50 #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs)
51 #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op)
52 #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr)
53 #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences)
54 #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
55 #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
56 #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
57 #define AMDGPU_GEM_DOMAIN_CPU 0x1
58 #define AMDGPU_GEM_DOMAIN_GTT 0x2
59 #define AMDGPU_GEM_DOMAIN_VRAM 0x4
60 #define AMDGPU_GEM_DOMAIN_GDS 0x8
61 #define AMDGPU_GEM_DOMAIN_GWS 0x10
62 #define AMDGPU_GEM_DOMAIN_OA 0x20
63 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | AMDGPU_GEM_DOMAIN_GTT | AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GDS | AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)
64 #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
65 #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1)
66 #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
67 #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
68 #define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
69 #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
70 #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6)
71 #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7)
72 #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8)
73 #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9)
74 struct drm_amdgpu_gem_create_in {
75   __u64 bo_size;
76   __u64 alignment;
77   __u64 domains;
78   __u64 domain_flags;
79 };
80 struct drm_amdgpu_gem_create_out {
81   __u32 handle;
82   __u32 _pad;
83 };
84 union drm_amdgpu_gem_create {
85   struct drm_amdgpu_gem_create_in in;
86   struct drm_amdgpu_gem_create_out out;
87 };
88 #define AMDGPU_BO_LIST_OP_CREATE 0
89 #define AMDGPU_BO_LIST_OP_DESTROY 1
90 #define AMDGPU_BO_LIST_OP_UPDATE 2
91 struct drm_amdgpu_bo_list_in {
92   __u32 operation;
93   __u32 list_handle;
94   __u32 bo_number;
95   __u32 bo_info_size;
96   __u64 bo_info_ptr;
97 };
98 struct drm_amdgpu_bo_list_entry {
99   __u32 bo_handle;
100   __u32 bo_priority;
101 };
102 struct drm_amdgpu_bo_list_out {
103   __u32 list_handle;
104   __u32 _pad;
105 };
106 union drm_amdgpu_bo_list {
107   struct drm_amdgpu_bo_list_in in;
108   struct drm_amdgpu_bo_list_out out;
109 };
110 #define AMDGPU_CTX_OP_ALLOC_CTX 1
111 #define AMDGPU_CTX_OP_FREE_CTX 2
112 #define AMDGPU_CTX_OP_QUERY_STATE 3
113 #define AMDGPU_CTX_OP_QUERY_STATE2 4
114 #define AMDGPU_CTX_NO_RESET 0
115 #define AMDGPU_CTX_GUILTY_RESET 1
116 #define AMDGPU_CTX_INNOCENT_RESET 2
117 #define AMDGPU_CTX_UNKNOWN_RESET 3
118 #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1 << 0)
119 #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1 << 1)
120 #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1 << 2)
121 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1 << 3)
122 #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1 << 4)
123 #define AMDGPU_CTX_PRIORITY_UNSET - 2048
124 #define AMDGPU_CTX_PRIORITY_VERY_LOW - 1023
125 #define AMDGPU_CTX_PRIORITY_LOW - 512
126 #define AMDGPU_CTX_PRIORITY_NORMAL 0
127 #define AMDGPU_CTX_PRIORITY_HIGH 512
128 #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
129 struct drm_amdgpu_ctx_in {
130   __u32 op;
131   __u32 flags;
132   __u32 ctx_id;
133   __s32 priority;
134 };
135 union drm_amdgpu_ctx_out {
136   struct {
137     __u32 ctx_id;
138     __u32 _pad;
139   } alloc;
140   struct {
141     __u64 flags;
142     __u32 hangs;
143     __u32 reset_status;
144   } state;
145 };
146 union drm_amdgpu_ctx {
147   struct drm_amdgpu_ctx_in in;
148   union drm_amdgpu_ctx_out out;
149 };
150 #define AMDGPU_VM_OP_RESERVE_VMID 1
151 #define AMDGPU_VM_OP_UNRESERVE_VMID 2
152 struct drm_amdgpu_vm_in {
153   __u32 op;
154   __u32 flags;
155 };
156 struct drm_amdgpu_vm_out {
157   __u64 flags;
158 };
159 union drm_amdgpu_vm {
160   struct drm_amdgpu_vm_in in;
161   struct drm_amdgpu_vm_out out;
162 };
163 #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1
164 #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2
165 struct drm_amdgpu_sched_in {
166   __u32 op;
167   __u32 fd;
168   __s32 priority;
169   __u32 ctx_id;
170 };
171 union drm_amdgpu_sched {
172   struct drm_amdgpu_sched_in in;
173 };
174 #define AMDGPU_GEM_USERPTR_READONLY (1 << 0)
175 #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
176 #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
177 #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
178 struct drm_amdgpu_gem_userptr {
179   __u64 addr;
180   __u64 size;
181   __u32 flags;
182   __u32 handle;
183 };
184 #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
185 #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf
186 #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4
187 #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f
188 #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9
189 #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7
190 #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12
191 #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7
192 #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15
193 #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3
194 #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17
195 #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3
196 #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19
197 #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3
198 #define AMDGPU_TILING_NUM_BANKS_SHIFT 21
199 #define AMDGPU_TILING_NUM_BANKS_MASK 0x3
200 #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
201 #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
202 #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
203 #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF
204 #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29
205 #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
206 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
207 #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
208 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
209 #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
210 #define AMDGPU_TILING_SCANOUT_SHIFT 63
211 #define AMDGPU_TILING_SCANOUT_MASK 0x1
212 #define AMDGPU_TILING_SET(field,value) (((__u64) (value) & AMDGPU_TILING_ ##field ##_MASK) << AMDGPU_TILING_ ##field ##_SHIFT)
213 #define AMDGPU_TILING_GET(value,field) (((__u64) (value) >> AMDGPU_TILING_ ##field ##_SHIFT) & AMDGPU_TILING_ ##field ##_MASK)
214 #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1
215 #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2
216 struct drm_amdgpu_gem_metadata {
217   __u32 handle;
218   __u32 op;
219   struct {
220     __u64 flags;
221     __u64 tiling_info;
222     __u32 data_size_bytes;
223     __u32 data[64];
224   } data;
225 };
226 struct drm_amdgpu_gem_mmap_in {
227   __u32 handle;
228   __u32 _pad;
229 };
230 struct drm_amdgpu_gem_mmap_out {
231   __u64 addr_ptr;
232 };
233 union drm_amdgpu_gem_mmap {
234   struct drm_amdgpu_gem_mmap_in in;
235   struct drm_amdgpu_gem_mmap_out out;
236 };
237 struct drm_amdgpu_gem_wait_idle_in {
238   __u32 handle;
239   __u32 flags;
240   __u64 timeout;
241 };
242 struct drm_amdgpu_gem_wait_idle_out {
243   __u32 status;
244   __u32 domain;
245 };
246 union drm_amdgpu_gem_wait_idle {
247   struct drm_amdgpu_gem_wait_idle_in in;
248   struct drm_amdgpu_gem_wait_idle_out out;
249 };
250 struct drm_amdgpu_wait_cs_in {
251   __u64 handle;
252   __u64 timeout;
253   __u32 ip_type;
254   __u32 ip_instance;
255   __u32 ring;
256   __u32 ctx_id;
257 };
258 struct drm_amdgpu_wait_cs_out {
259   __u64 status;
260 };
261 union drm_amdgpu_wait_cs {
262   struct drm_amdgpu_wait_cs_in in;
263   struct drm_amdgpu_wait_cs_out out;
264 };
265 struct drm_amdgpu_fence {
266   __u32 ctx_id;
267   __u32 ip_type;
268   __u32 ip_instance;
269   __u32 ring;
270   __u64 seq_no;
271 };
272 struct drm_amdgpu_wait_fences_in {
273   __u64 fences;
274   __u32 fence_count;
275   __u32 wait_all;
276   __u64 timeout_ns;
277 };
278 struct drm_amdgpu_wait_fences_out {
279   __u32 status;
280   __u32 first_signaled;
281 };
282 union drm_amdgpu_wait_fences {
283   struct drm_amdgpu_wait_fences_in in;
284   struct drm_amdgpu_wait_fences_out out;
285 };
286 #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0
287 #define AMDGPU_GEM_OP_SET_PLACEMENT 1
288 struct drm_amdgpu_gem_op {
289   __u32 handle;
290   __u32 op;
291   __u64 value;
292 };
293 #define AMDGPU_VA_OP_MAP 1
294 #define AMDGPU_VA_OP_UNMAP 2
295 #define AMDGPU_VA_OP_CLEAR 3
296 #define AMDGPU_VA_OP_REPLACE 4
297 #define AMDGPU_VM_DELAY_UPDATE (1 << 0)
298 #define AMDGPU_VM_PAGE_READABLE (1 << 1)
299 #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2)
300 #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3)
301 #define AMDGPU_VM_PAGE_PRT (1 << 4)
302 #define AMDGPU_VM_MTYPE_MASK (0xf << 5)
303 #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
304 #define AMDGPU_VM_MTYPE_NC (1 << 5)
305 #define AMDGPU_VM_MTYPE_WC (2 << 5)
306 #define AMDGPU_VM_MTYPE_CC (3 << 5)
307 #define AMDGPU_VM_MTYPE_UC (4 << 5)
308 #define AMDGPU_VM_MTYPE_RW (5 << 5)
309 struct drm_amdgpu_gem_va {
310   __u32 handle;
311   __u32 _pad;
312   __u32 operation;
313   __u32 flags;
314   __u64 va_address;
315   __u64 offset_in_bo;
316   __u64 map_size;
317 };
318 #define AMDGPU_HW_IP_GFX 0
319 #define AMDGPU_HW_IP_COMPUTE 1
320 #define AMDGPU_HW_IP_DMA 2
321 #define AMDGPU_HW_IP_UVD 3
322 #define AMDGPU_HW_IP_VCE 4
323 #define AMDGPU_HW_IP_UVD_ENC 5
324 #define AMDGPU_HW_IP_VCN_DEC 6
325 #define AMDGPU_HW_IP_VCN_ENC 7
326 #define AMDGPU_HW_IP_VCN_JPEG 8
327 #define AMDGPU_HW_IP_NUM 9
328 #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
329 #define AMDGPU_CHUNK_ID_IB 0x01
330 #define AMDGPU_CHUNK_ID_FENCE 0x02
331 #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03
332 #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04
333 #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05
334 #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06
335 #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
336 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
337 #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
338 struct drm_amdgpu_cs_chunk {
339   __u32 chunk_id;
340   __u32 length_dw;
341   __u64 chunk_data;
342 };
343 struct drm_amdgpu_cs_in {
344   __u32 ctx_id;
345   __u32 bo_list_handle;
346   __u32 num_chunks;
347   __u32 _pad;
348   __u64 chunks;
349 };
350 struct drm_amdgpu_cs_out {
351   __u64 handle;
352 };
353 union drm_amdgpu_cs {
354   struct drm_amdgpu_cs_in in;
355   struct drm_amdgpu_cs_out out;
356 };
357 #define AMDGPU_IB_FLAG_CE (1 << 0)
358 #define AMDGPU_IB_FLAG_PREAMBLE (1 << 1)
359 #define AMDGPU_IB_FLAG_PREEMPT (1 << 2)
360 #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3)
361 #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4)
362 struct drm_amdgpu_cs_chunk_ib {
363   __u32 _pad;
364   __u32 flags;
365   __u64 va_start;
366   __u32 ib_bytes;
367   __u32 ip_type;
368   __u32 ip_instance;
369   __u32 ring;
370 };
371 struct drm_amdgpu_cs_chunk_dep {
372   __u32 ip_type;
373   __u32 ip_instance;
374   __u32 ring;
375   __u32 ctx_id;
376   __u64 handle;
377 };
378 struct drm_amdgpu_cs_chunk_fence {
379   __u32 handle;
380   __u32 offset;
381 };
382 struct drm_amdgpu_cs_chunk_sem {
383   __u32 handle;
384 };
385 struct drm_amdgpu_cs_chunk_syncobj {
386   __u32 handle;
387   __u32 flags;
388   __u64 point;
389 };
390 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0
391 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1
392 #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2
393 union drm_amdgpu_fence_to_handle {
394   struct {
395     struct drm_amdgpu_fence fence;
396     __u32 what;
397     __u32 pad;
398   } in;
399   struct {
400     __u32 handle;
401   } out;
402 };
403 struct drm_amdgpu_cs_chunk_data {
404   union {
405     struct drm_amdgpu_cs_chunk_ib ib_data;
406     struct drm_amdgpu_cs_chunk_fence fence_data;
407   };
408 };
409 #define AMDGPU_IDS_FLAGS_FUSION 0x1
410 #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2
411 #define AMDGPU_INFO_ACCEL_WORKING 0x00
412 #define AMDGPU_INFO_CRTC_FROM_ID 0x01
413 #define AMDGPU_INFO_HW_IP_INFO 0x02
414 #define AMDGPU_INFO_HW_IP_COUNT 0x03
415 #define AMDGPU_INFO_TIMESTAMP 0x05
416 #define AMDGPU_INFO_FW_VERSION 0x0e
417 #define AMDGPU_INFO_FW_VCE 0x1
418 #define AMDGPU_INFO_FW_UVD 0x2
419 #define AMDGPU_INFO_FW_GMC 0x03
420 #define AMDGPU_INFO_FW_GFX_ME 0x04
421 #define AMDGPU_INFO_FW_GFX_PFP 0x05
422 #define AMDGPU_INFO_FW_GFX_CE 0x06
423 #define AMDGPU_INFO_FW_GFX_RLC 0x07
424 #define AMDGPU_INFO_FW_GFX_MEC 0x08
425 #define AMDGPU_INFO_FW_SMC 0x0a
426 #define AMDGPU_INFO_FW_SDMA 0x0b
427 #define AMDGPU_INFO_FW_SOS 0x0c
428 #define AMDGPU_INFO_FW_ASD 0x0d
429 #define AMDGPU_INFO_FW_VCN 0x0e
430 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f
431 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10
432 #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11
433 #define AMDGPU_INFO_FW_DMCU 0x12
434 #define AMDGPU_INFO_FW_TA 0x13
435 #define AMDGPU_INFO_FW_DMCUB 0x14
436 #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
437 #define AMDGPU_INFO_VRAM_USAGE 0x10
438 #define AMDGPU_INFO_GTT_USAGE 0x11
439 #define AMDGPU_INFO_GDS_CONFIG 0x13
440 #define AMDGPU_INFO_VRAM_GTT 0x14
441 #define AMDGPU_INFO_READ_MMR_REG 0x15
442 #define AMDGPU_INFO_DEV_INFO 0x16
443 #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17
444 #define AMDGPU_INFO_NUM_EVICTIONS 0x18
445 #define AMDGPU_INFO_MEMORY 0x19
446 #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A
447 #define AMDGPU_INFO_VBIOS 0x1B
448 #define AMDGPU_INFO_VBIOS_SIZE 0x1
449 #define AMDGPU_INFO_VBIOS_IMAGE 0x2
450 #define AMDGPU_INFO_NUM_HANDLES 0x1C
451 #define AMDGPU_INFO_SENSOR 0x1D
452 #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1
453 #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2
454 #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3
455 #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4
456 #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5
457 #define AMDGPU_INFO_SENSOR_VDDNB 0x6
458 #define AMDGPU_INFO_SENSOR_VDDGFX 0x7
459 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
460 #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
461 #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
462 #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
463 #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
464 #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
465 #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1)
466 #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2)
467 #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3)
468 #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4)
469 #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5)
470 #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6)
471 #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7)
472 #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8)
473 #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9)
474 #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10)
475 #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11)
476 #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
477 #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
478 #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
479 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
480 #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8
481 #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff
482 struct drm_amdgpu_query_fw {
483   __u32 fw_type;
484   __u32 ip_instance;
485   __u32 index;
486   __u32 _pad;
487 };
488 struct drm_amdgpu_info {
489   __u64 return_pointer;
490   __u32 return_size;
491   __u32 query;
492   union {
493     struct {
494       __u32 id;
495       __u32 _pad;
496     } mode_crtc;
497     struct {
498       __u32 type;
499       __u32 ip_instance;
500     } query_hw_ip;
501     struct {
502       __u32 dword_offset;
503       __u32 count;
504       __u32 instance;
505       __u32 flags;
506     } read_mmr_reg;
507     struct drm_amdgpu_query_fw query_fw;
508     struct {
509       __u32 type;
510       __u32 offset;
511     } vbios_info;
512     struct {
513       __u32 type;
514     } sensor_info;
515   };
516 };
517 struct drm_amdgpu_info_gds {
518   __u32 gds_gfx_partition_size;
519   __u32 compute_partition_size;
520   __u32 gds_total_size;
521   __u32 gws_per_gfx_partition;
522   __u32 gws_per_compute_partition;
523   __u32 oa_per_gfx_partition;
524   __u32 oa_per_compute_partition;
525   __u32 _pad;
526 };
527 struct drm_amdgpu_info_vram_gtt {
528   __u64 vram_size;
529   __u64 vram_cpu_accessible_size;
530   __u64 gtt_size;
531 };
532 struct drm_amdgpu_heap_info {
533   __u64 total_heap_size;
534   __u64 usable_heap_size;
535   __u64 heap_usage;
536   __u64 max_allocation;
537 };
538 struct drm_amdgpu_memory_info {
539   struct drm_amdgpu_heap_info vram;
540   struct drm_amdgpu_heap_info cpu_accessible_vram;
541   struct drm_amdgpu_heap_info gtt;
542 };
543 struct drm_amdgpu_info_firmware {
544   __u32 ver;
545   __u32 feature;
546 };
547 #define AMDGPU_VRAM_TYPE_UNKNOWN 0
548 #define AMDGPU_VRAM_TYPE_GDDR1 1
549 #define AMDGPU_VRAM_TYPE_DDR2 2
550 #define AMDGPU_VRAM_TYPE_GDDR3 3
551 #define AMDGPU_VRAM_TYPE_GDDR4 4
552 #define AMDGPU_VRAM_TYPE_GDDR5 5
553 #define AMDGPU_VRAM_TYPE_HBM 6
554 #define AMDGPU_VRAM_TYPE_DDR3 7
555 #define AMDGPU_VRAM_TYPE_DDR4 8
556 #define AMDGPU_VRAM_TYPE_GDDR6 9
557 struct drm_amdgpu_info_device {
558   __u32 device_id;
559   __u32 chip_rev;
560   __u32 external_rev;
561   __u32 pci_rev;
562   __u32 family;
563   __u32 num_shader_engines;
564   __u32 num_shader_arrays_per_engine;
565   __u32 gpu_counter_freq;
566   __u64 max_engine_clock;
567   __u64 max_memory_clock;
568   __u32 cu_active_number;
569   __u32 cu_ao_mask;
570   __u32 cu_bitmap[4][4];
571   __u32 enabled_rb_pipes_mask;
572   __u32 num_rb_pipes;
573   __u32 num_hw_gfx_contexts;
574   __u32 _pad;
575   __u64 ids_flags;
576   __u64 virtual_address_offset;
577   __u64 virtual_address_max;
578   __u32 virtual_address_alignment;
579   __u32 pte_fragment_size;
580   __u32 gart_page_size;
581   __u32 ce_ram_size;
582   __u32 vram_type;
583   __u32 vram_bit_width;
584   __u32 vce_harvest_config;
585   __u32 gc_double_offchip_lds_buf;
586   __u64 prim_buf_gpu_addr;
587   __u64 pos_buf_gpu_addr;
588   __u64 cntl_sb_buf_gpu_addr;
589   __u64 param_buf_gpu_addr;
590   __u32 prim_buf_size;
591   __u32 pos_buf_size;
592   __u32 cntl_sb_buf_size;
593   __u32 param_buf_size;
594   __u32 wave_front_size;
595   __u32 num_shader_visible_vgprs;
596   __u32 num_cu_per_sh;
597   __u32 num_tcc_blocks;
598   __u32 gs_vgt_table_depth;
599   __u32 gs_prim_buffer_depth;
600   __u32 max_gs_waves_per_vgt;
601   __u32 _pad1;
602   __u32 cu_ao_bitmap[4][4];
603   __u64 high_va_offset;
604   __u64 high_va_max;
605   __u32 pa_sc_tile_steering_override;
606   __u64 tcc_disabled_mask;
607 };
608 struct drm_amdgpu_info_hw_ip {
609   __u32 hw_ip_version_major;
610   __u32 hw_ip_version_minor;
611   __u64 capabilities_flags;
612   __u32 ib_start_alignment;
613   __u32 ib_size_alignment;
614   __u32 available_rings;
615   __u32 _pad;
616 };
617 struct drm_amdgpu_info_num_handles {
618   __u32 uvd_max_handles;
619   __u32 uvd_used_handles;
620 };
621 #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6
622 struct drm_amdgpu_info_vce_clock_table_entry {
623   __u32 sclk;
624   __u32 mclk;
625   __u32 eclk;
626   __u32 pad;
627 };
628 struct drm_amdgpu_info_vce_clock_table {
629   struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES];
630   __u32 num_valid_entries;
631   __u32 pad;
632 };
633 #define AMDGPU_FAMILY_UNKNOWN 0
634 #define AMDGPU_FAMILY_SI 110
635 #define AMDGPU_FAMILY_CI 120
636 #define AMDGPU_FAMILY_KV 125
637 #define AMDGPU_FAMILY_VI 130
638 #define AMDGPU_FAMILY_CZ 135
639 #define AMDGPU_FAMILY_AI 141
640 #define AMDGPU_FAMILY_RV 142
641 #define AMDGPU_FAMILY_NV 143
642 #ifdef __cplusplus
643 }
644 #endif
645 #endif
646