1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef HABANALABS_H_ 20 #define HABANALABS_H_ 21 #include <linux/types.h> 22 #include <linux/ioctl.h> 23 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 24 enum goya_queue_id { 25 GOYA_QUEUE_ID_DMA_0 = 0, 26 GOYA_QUEUE_ID_DMA_1 = 1, 27 GOYA_QUEUE_ID_DMA_2 = 2, 28 GOYA_QUEUE_ID_DMA_3 = 3, 29 GOYA_QUEUE_ID_DMA_4 = 4, 30 GOYA_QUEUE_ID_CPU_PQ = 5, 31 GOYA_QUEUE_ID_MME = 6, 32 GOYA_QUEUE_ID_TPC0 = 7, 33 GOYA_QUEUE_ID_TPC1 = 8, 34 GOYA_QUEUE_ID_TPC2 = 9, 35 GOYA_QUEUE_ID_TPC3 = 10, 36 GOYA_QUEUE_ID_TPC4 = 11, 37 GOYA_QUEUE_ID_TPC5 = 12, 38 GOYA_QUEUE_ID_TPC6 = 13, 39 GOYA_QUEUE_ID_TPC7 = 14, 40 GOYA_QUEUE_ID_SIZE 41 }; 42 enum goya_engine_id { 43 GOYA_ENGINE_ID_DMA_0 = 0, 44 GOYA_ENGINE_ID_DMA_1, 45 GOYA_ENGINE_ID_DMA_2, 46 GOYA_ENGINE_ID_DMA_3, 47 GOYA_ENGINE_ID_DMA_4, 48 GOYA_ENGINE_ID_MME_0, 49 GOYA_ENGINE_ID_TPC_0, 50 GOYA_ENGINE_ID_TPC_1, 51 GOYA_ENGINE_ID_TPC_2, 52 GOYA_ENGINE_ID_TPC_3, 53 GOYA_ENGINE_ID_TPC_4, 54 GOYA_ENGINE_ID_TPC_5, 55 GOYA_ENGINE_ID_TPC_6, 56 GOYA_ENGINE_ID_TPC_7, 57 GOYA_ENGINE_ID_SIZE 58 }; 59 enum hl_device_status { 60 HL_DEVICE_STATUS_OPERATIONAL, 61 HL_DEVICE_STATUS_IN_RESET, 62 HL_DEVICE_STATUS_MALFUNCTION 63 }; 64 #define HL_INFO_HW_IP_INFO 0 65 #define HL_INFO_HW_EVENTS 1 66 #define HL_INFO_DRAM_USAGE 2 67 #define HL_INFO_HW_IDLE 3 68 #define HL_INFO_DEVICE_STATUS 4 69 #define HL_INFO_DEVICE_UTILIZATION 6 70 #define HL_INFO_HW_EVENTS_AGGREGATE 7 71 #define HL_INFO_CLK_RATE 8 72 #define HL_INFO_RESET_COUNT 9 73 #define HL_INFO_VERSION_MAX_LEN 128 74 #define HL_INFO_CARD_NAME_MAX_LEN 16 75 struct hl_info_hw_ip_info { 76 __u64 sram_base_address; 77 __u64 dram_base_address; 78 __u64 dram_size; 79 __u32 sram_size; 80 __u32 num_of_events; 81 __u32 device_id; 82 __u32 reserved[3]; 83 __u32 armcp_cpld_version; 84 __u32 psoc_pci_pll_nr; 85 __u32 psoc_pci_pll_nf; 86 __u32 psoc_pci_pll_od; 87 __u32 psoc_pci_pll_div_factor; 88 __u8 tpc_enabled_mask; 89 __u8 dram_enabled; 90 __u8 pad[2]; 91 __u8 armcp_version[HL_INFO_VERSION_MAX_LEN]; 92 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 93 }; 94 struct hl_info_dram_usage { 95 __u64 dram_free_mem; 96 __u64 ctx_dram_mem; 97 }; 98 struct hl_info_hw_idle { 99 __u32 is_idle; 100 __u32 busy_engines_mask; 101 }; 102 struct hl_info_device_status { 103 __u32 status; 104 __u32 pad; 105 }; 106 struct hl_info_device_utilization { 107 __u32 utilization; 108 __u32 pad; 109 }; 110 struct hl_info_clk_rate { 111 __u32 cur_clk_rate_mhz; 112 __u32 max_clk_rate_mhz; 113 }; 114 struct hl_info_reset_count { 115 __u32 hard_reset_cnt; 116 __u32 soft_reset_cnt; 117 }; 118 struct hl_info_args { 119 __u64 return_pointer; 120 __u32 return_size; 121 __u32 op; 122 union { 123 __u32 ctx_id; 124 __u32 period_ms; 125 }; 126 __u32 pad; 127 }; 128 #define HL_CB_OP_CREATE 0 129 #define HL_CB_OP_DESTROY 1 130 #define HL_MAX_CB_SIZE 0x200000 131 struct hl_cb_in { 132 __u64 cb_handle; 133 __u32 op; 134 __u32 cb_size; 135 __u32 ctx_id; 136 __u32 pad; 137 }; 138 struct hl_cb_out { 139 __u64 cb_handle; 140 }; 141 union hl_cb_args { 142 struct hl_cb_in in; 143 struct hl_cb_out out; 144 }; 145 struct hl_cs_chunk { 146 __u64 cb_handle; 147 __u32 queue_index; 148 __u32 cb_size; 149 __u32 cs_chunk_flags; 150 __u32 pad[11]; 151 }; 152 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 153 #define HL_CS_STATUS_SUCCESS 0 154 #define HL_MAX_JOBS_PER_CS 512 155 struct hl_cs_in { 156 __u64 chunks_restore; 157 __u64 chunks_execute; 158 __u64 chunks_store; 159 __u32 num_chunks_restore; 160 __u32 num_chunks_execute; 161 __u32 num_chunks_store; 162 __u32 cs_flags; 163 __u32 ctx_id; 164 }; 165 struct hl_cs_out { 166 __u64 seq; 167 __u32 status; 168 __u32 pad; 169 }; 170 union hl_cs_args { 171 struct hl_cs_in in; 172 struct hl_cs_out out; 173 }; 174 struct hl_wait_cs_in { 175 __u64 seq; 176 __u64 timeout_us; 177 __u32 ctx_id; 178 __u32 pad; 179 }; 180 #define HL_WAIT_CS_STATUS_COMPLETED 0 181 #define HL_WAIT_CS_STATUS_BUSY 1 182 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 183 #define HL_WAIT_CS_STATUS_ABORTED 3 184 #define HL_WAIT_CS_STATUS_INTERRUPTED 4 185 struct hl_wait_cs_out { 186 __u32 status; 187 __u32 pad; 188 }; 189 union hl_wait_cs_args { 190 struct hl_wait_cs_in in; 191 struct hl_wait_cs_out out; 192 }; 193 #define HL_MEM_OP_ALLOC 0 194 #define HL_MEM_OP_FREE 1 195 #define HL_MEM_OP_MAP 2 196 #define HL_MEM_OP_UNMAP 3 197 #define HL_MEM_CONTIGUOUS 0x1 198 #define HL_MEM_SHARED 0x2 199 #define HL_MEM_USERPTR 0x4 200 struct hl_mem_in { 201 union { 202 struct { 203 __u64 mem_size; 204 } alloc; 205 struct { 206 __u64 handle; 207 } free; 208 struct { 209 __u64 hint_addr; 210 __u64 handle; 211 } map_device; 212 struct { 213 __u64 host_virt_addr; 214 __u64 hint_addr; 215 __u64 mem_size; 216 } map_host; 217 struct { 218 __u64 device_virt_addr; 219 } unmap; 220 }; 221 __u32 op; 222 __u32 flags; 223 __u32 ctx_id; 224 __u32 pad; 225 }; 226 struct hl_mem_out { 227 union { 228 __u64 device_virt_addr; 229 __u64 handle; 230 }; 231 }; 232 union hl_mem_args { 233 struct hl_mem_in in; 234 struct hl_mem_out out; 235 }; 236 #define HL_DEBUG_MAX_AUX_VALUES 10 237 struct hl_debug_params_etr { 238 __u64 buffer_address; 239 __u64 buffer_size; 240 __u32 sink_mode; 241 __u32 pad; 242 }; 243 struct hl_debug_params_etf { 244 __u64 buffer_address; 245 __u64 buffer_size; 246 __u32 sink_mode; 247 __u32 pad; 248 }; 249 struct hl_debug_params_stm { 250 __u64 he_mask; 251 __u64 sp_mask; 252 __u32 id; 253 __u32 frequency; 254 }; 255 struct hl_debug_params_bmon { 256 __u64 start_addr0; 257 __u64 addr_mask0; 258 __u64 start_addr1; 259 __u64 addr_mask1; 260 __u32 bw_win; 261 __u32 win_capture; 262 __u32 id; 263 __u32 pad; 264 }; 265 struct hl_debug_params_spmu { 266 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 267 __u32 event_types_num; 268 __u32 pad; 269 }; 270 #define HL_DEBUG_OP_ETR 0 271 #define HL_DEBUG_OP_ETF 1 272 #define HL_DEBUG_OP_STM 2 273 #define HL_DEBUG_OP_FUNNEL 3 274 #define HL_DEBUG_OP_BMON 4 275 #define HL_DEBUG_OP_SPMU 5 276 #define HL_DEBUG_OP_TIMESTAMP 6 277 #define HL_DEBUG_OP_SET_MODE 7 278 struct hl_debug_args { 279 __u64 input_ptr; 280 __u64 output_ptr; 281 __u32 input_size; 282 __u32 output_size; 283 __u32 op; 284 __u32 reg_idx; 285 __u32 enable; 286 __u32 ctx_id; 287 }; 288 #define HL_IOCTL_INFO _IOWR('H', 0x01, struct hl_info_args) 289 #define HL_IOCTL_CB _IOWR('H', 0x02, union hl_cb_args) 290 #define HL_IOCTL_CS _IOWR('H', 0x03, union hl_cs_args) 291 #define HL_IOCTL_WAIT_CS _IOWR('H', 0x04, union hl_wait_cs_args) 292 #define HL_IOCTL_MEMORY _IOWR('H', 0x05, union hl_mem_args) 293 #define HL_IOCTL_DEBUG _IOWR('H', 0x06, struct hl_debug_args) 294 #define HL_COMMAND_START 0x01 295 #define HL_COMMAND_END 0x07 296 #endif 297