1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef KFD_IOCTL_H_INCLUDED 20 #define KFD_IOCTL_H_INCLUDED 21 #include <drm/drm.h> 22 #include <linux/ioctl.h> 23 #define KFD_IOCTL_MAJOR_VERSION 1 24 #define KFD_IOCTL_MINOR_VERSION 1 25 struct kfd_ioctl_get_version_args { 26 __u32 major_version; 27 __u32 minor_version; 28 }; 29 #define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0 30 #define KFD_IOC_QUEUE_TYPE_SDMA 0x1 31 #define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2 32 #define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3 33 #define KFD_MAX_QUEUE_PERCENTAGE 100 34 #define KFD_MAX_QUEUE_PRIORITY 15 35 struct kfd_ioctl_create_queue_args { 36 __u64 ring_base_address; 37 __u64 write_pointer_address; 38 __u64 read_pointer_address; 39 __u64 doorbell_offset; 40 __u32 ring_size; 41 __u32 gpu_id; 42 __u32 queue_type; 43 __u32 queue_percentage; 44 __u32 queue_priority; 45 __u32 queue_id; 46 __u64 eop_buffer_address; 47 __u64 eop_buffer_size; 48 __u64 ctx_save_restore_address; 49 __u32 ctx_save_restore_size; 50 __u32 ctl_stack_size; 51 }; 52 struct kfd_ioctl_destroy_queue_args { 53 __u32 queue_id; 54 __u32 pad; 55 }; 56 struct kfd_ioctl_update_queue_args { 57 __u64 ring_base_address; 58 __u32 queue_id; 59 __u32 ring_size; 60 __u32 queue_percentage; 61 __u32 queue_priority; 62 }; 63 struct kfd_ioctl_set_cu_mask_args { 64 __u32 queue_id; 65 __u32 num_cu_mask; 66 __u64 cu_mask_ptr; 67 }; 68 struct kfd_ioctl_get_queue_wave_state_args { 69 __u64 ctl_stack_address; 70 __u32 ctl_stack_used_size; 71 __u32 save_area_used_size; 72 __u32 queue_id; 73 __u32 pad; 74 }; 75 #define KFD_IOC_CACHE_POLICY_COHERENT 0 76 #define KFD_IOC_CACHE_POLICY_NONCOHERENT 1 77 struct kfd_ioctl_set_memory_policy_args { 78 __u64 alternate_aperture_base; 79 __u64 alternate_aperture_size; 80 __u32 gpu_id; 81 __u32 default_policy; 82 __u32 alternate_policy; 83 __u32 pad; 84 }; 85 struct kfd_ioctl_get_clock_counters_args { 86 __u64 gpu_clock_counter; 87 __u64 cpu_clock_counter; 88 __u64 system_clock_counter; 89 __u64 system_clock_freq; 90 __u32 gpu_id; 91 __u32 pad; 92 }; 93 struct kfd_process_device_apertures { 94 __u64 lds_base; 95 __u64 lds_limit; 96 __u64 scratch_base; 97 __u64 scratch_limit; 98 __u64 gpuvm_base; 99 __u64 gpuvm_limit; 100 __u32 gpu_id; 101 __u32 pad; 102 }; 103 #define NUM_OF_SUPPORTED_GPUS 7 104 struct kfd_ioctl_get_process_apertures_args { 105 struct kfd_process_device_apertures process_apertures[NUM_OF_SUPPORTED_GPUS]; 106 __u32 num_of_nodes; 107 __u32 pad; 108 }; 109 struct kfd_ioctl_get_process_apertures_new_args { 110 __u64 kfd_process_device_apertures_ptr; 111 __u32 num_of_nodes; 112 __u32 pad; 113 }; 114 #define MAX_ALLOWED_NUM_POINTS 100 115 #define MAX_ALLOWED_AW_BUFF_SIZE 4096 116 #define MAX_ALLOWED_WAC_BUFF_SIZE 128 117 struct kfd_ioctl_dbg_register_args { 118 __u32 gpu_id; 119 __u32 pad; 120 }; 121 struct kfd_ioctl_dbg_unregister_args { 122 __u32 gpu_id; 123 __u32 pad; 124 }; 125 struct kfd_ioctl_dbg_address_watch_args { 126 __u64 content_ptr; 127 __u32 gpu_id; 128 __u32 buf_size_in_bytes; 129 }; 130 struct kfd_ioctl_dbg_wave_control_args { 131 __u64 content_ptr; 132 __u32 gpu_id; 133 __u32 buf_size_in_bytes; 134 }; 135 #define KFD_IOC_EVENT_SIGNAL 0 136 #define KFD_IOC_EVENT_NODECHANGE 1 137 #define KFD_IOC_EVENT_DEVICESTATECHANGE 2 138 #define KFD_IOC_EVENT_HW_EXCEPTION 3 139 #define KFD_IOC_EVENT_SYSTEM_EVENT 4 140 #define KFD_IOC_EVENT_DEBUG_EVENT 5 141 #define KFD_IOC_EVENT_PROFILE_EVENT 6 142 #define KFD_IOC_EVENT_QUEUE_EVENT 7 143 #define KFD_IOC_EVENT_MEMORY 8 144 #define KFD_IOC_WAIT_RESULT_COMPLETE 0 145 #define KFD_IOC_WAIT_RESULT_TIMEOUT 1 146 #define KFD_IOC_WAIT_RESULT_FAIL 2 147 #define KFD_SIGNAL_EVENT_LIMIT 4096 148 #define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0 149 #define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1 150 #define KFD_HW_EXCEPTION_GPU_HANG 0 151 #define KFD_HW_EXCEPTION_ECC 1 152 #define KFD_MEM_ERR_NO_RAS 0 153 #define KFD_MEM_ERR_SRAM_ECC 1 154 #define KFD_MEM_ERR_POISON_CONSUMED 2 155 #define KFD_MEM_ERR_GPU_HANG 3 156 struct kfd_ioctl_create_event_args { 157 __u64 event_page_offset; 158 __u32 event_trigger_data; 159 __u32 event_type; 160 __u32 auto_reset; 161 __u32 node_id; 162 __u32 event_id; 163 __u32 event_slot_index; 164 }; 165 struct kfd_ioctl_destroy_event_args { 166 __u32 event_id; 167 __u32 pad; 168 }; 169 struct kfd_ioctl_set_event_args { 170 __u32 event_id; 171 __u32 pad; 172 }; 173 struct kfd_ioctl_reset_event_args { 174 __u32 event_id; 175 __u32 pad; 176 }; 177 struct kfd_memory_exception_failure { 178 __u32 NotPresent; 179 __u32 ReadOnly; 180 __u32 NoExecute; 181 __u32 imprecise; 182 }; 183 struct kfd_hsa_memory_exception_data { 184 struct kfd_memory_exception_failure failure; 185 __u64 va; 186 __u32 gpu_id; 187 __u32 ErrorType; 188 }; 189 struct kfd_hsa_hw_exception_data { 190 __u32 reset_type; 191 __u32 reset_cause; 192 __u32 memory_lost; 193 __u32 gpu_id; 194 }; 195 struct kfd_event_data { 196 union { 197 struct kfd_hsa_memory_exception_data memory_exception_data; 198 struct kfd_hsa_hw_exception_data hw_exception_data; 199 }; 200 __u64 kfd_event_data_ext; 201 __u32 event_id; 202 __u32 pad; 203 }; 204 struct kfd_ioctl_wait_events_args { 205 __u64 events_ptr; 206 __u32 num_events; 207 __u32 wait_for_all; 208 __u32 timeout; 209 __u32 wait_result; 210 }; 211 struct kfd_ioctl_set_scratch_backing_va_args { 212 __u64 va_addr; 213 __u32 gpu_id; 214 __u32 pad; 215 }; 216 struct kfd_ioctl_get_tile_config_args { 217 __u64 tile_config_ptr; 218 __u64 macro_tile_config_ptr; 219 __u32 num_tile_configs; 220 __u32 num_macro_tile_configs; 221 __u32 gpu_id; 222 __u32 gb_addr_config; 223 __u32 num_banks; 224 __u32 num_ranks; 225 }; 226 struct kfd_ioctl_set_trap_handler_args { 227 __u64 tba_addr; 228 __u64 tma_addr; 229 __u32 gpu_id; 230 __u32 pad; 231 }; 232 struct kfd_ioctl_acquire_vm_args { 233 __u32 drm_fd; 234 __u32 gpu_id; 235 }; 236 #define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0) 237 #define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1) 238 #define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2) 239 #define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3) 240 #define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4) 241 #define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31) 242 #define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30) 243 #define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29) 244 #define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28) 245 #define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27) 246 #define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26) 247 struct kfd_ioctl_alloc_memory_of_gpu_args { 248 __u64 va_addr; 249 __u64 size; 250 __u64 handle; 251 __u64 mmap_offset; 252 __u32 gpu_id; 253 __u32 flags; 254 }; 255 struct kfd_ioctl_free_memory_of_gpu_args { 256 __u64 handle; 257 }; 258 struct kfd_ioctl_map_memory_to_gpu_args { 259 __u64 handle; 260 __u64 device_ids_array_ptr; 261 __u32 n_devices; 262 __u32 n_success; 263 }; 264 struct kfd_ioctl_unmap_memory_from_gpu_args { 265 __u64 handle; 266 __u64 device_ids_array_ptr; 267 __u32 n_devices; 268 __u32 n_success; 269 }; 270 struct kfd_ioctl_get_dmabuf_info_args { 271 __u64 size; 272 __u64 metadata_ptr; 273 __u32 metadata_size; 274 __u32 gpu_id; 275 __u32 flags; 276 __u32 dmabuf_fd; 277 }; 278 struct kfd_ioctl_import_dmabuf_args { 279 __u64 va_addr; 280 __u64 handle; 281 __u32 gpu_id; 282 __u32 dmabuf_fd; 283 }; 284 enum kfd_mmio_remap { 285 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0, 286 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, 287 }; 288 #define AMDKFD_IOCTL_BASE 'K' 289 #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) 290 #define AMDKFD_IOR(nr,type) _IOR(AMDKFD_IOCTL_BASE, nr, type) 291 #define AMDKFD_IOW(nr,type) _IOW(AMDKFD_IOCTL_BASE, nr, type) 292 #define AMDKFD_IOWR(nr,type) _IOWR(AMDKFD_IOCTL_BASE, nr, type) 293 #define AMDKFD_IOC_GET_VERSION AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args) 294 #define AMDKFD_IOC_CREATE_QUEUE AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args) 295 #define AMDKFD_IOC_DESTROY_QUEUE AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args) 296 #define AMDKFD_IOC_SET_MEMORY_POLICY AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args) 297 #define AMDKFD_IOC_GET_CLOCK_COUNTERS AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args) 298 #define AMDKFD_IOC_GET_PROCESS_APERTURES AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args) 299 #define AMDKFD_IOC_UPDATE_QUEUE AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args) 300 #define AMDKFD_IOC_CREATE_EVENT AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args) 301 #define AMDKFD_IOC_DESTROY_EVENT AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args) 302 #define AMDKFD_IOC_SET_EVENT AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args) 303 #define AMDKFD_IOC_RESET_EVENT AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args) 304 #define AMDKFD_IOC_WAIT_EVENTS AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args) 305 #define AMDKFD_IOC_DBG_REGISTER AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args) 306 #define AMDKFD_IOC_DBG_UNREGISTER AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args) 307 #define AMDKFD_IOC_DBG_ADDRESS_WATCH AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args) 308 #define AMDKFD_IOC_DBG_WAVE_CONTROL AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args) 309 #define AMDKFD_IOC_SET_SCRATCH_BACKING_VA AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args) 310 #define AMDKFD_IOC_GET_TILE_CONFIG AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args) 311 #define AMDKFD_IOC_SET_TRAP_HANDLER AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args) 312 #define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW AMDKFD_IOWR(0x14, struct kfd_ioctl_get_process_apertures_new_args) 313 #define AMDKFD_IOC_ACQUIRE_VM AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args) 314 #define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args) 315 #define AMDKFD_IOC_FREE_MEMORY_OF_GPU AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args) 316 #define AMDKFD_IOC_MAP_MEMORY_TO_GPU AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args) 317 #define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args) 318 #define AMDKFD_IOC_SET_CU_MASK AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args) 319 #define AMDKFD_IOC_GET_QUEUE_WAVE_STATE AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args) 320 #define AMDKFD_IOC_GET_DMABUF_INFO AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args) 321 #define AMDKFD_IOC_IMPORT_DMABUF AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args) 322 #define AMDKFD_COMMAND_START 0x01 323 #define AMDKFD_COMMAND_END 0x1E 324 #endif 325