1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef _UAPI__LINUX_MDIO_H__ 20 #define _UAPI__LINUX_MDIO_H__ 21 #include <linux/types.h> 22 #include <linux/mii.h> 23 #define MDIO_MMD_PMAPMD 1 24 #define MDIO_MMD_WIS 2 25 #define MDIO_MMD_PCS 3 26 #define MDIO_MMD_PHYXS 4 27 #define MDIO_MMD_DTEXS 5 28 #define MDIO_MMD_TC 6 29 #define MDIO_MMD_AN 7 30 #define MDIO_MMD_C22EXT 29 31 #define MDIO_MMD_VEND1 30 32 #define MDIO_MMD_VEND2 31 33 #define MDIO_CTRL1 MII_BMCR 34 #define MDIO_STAT1 MII_BMSR 35 #define MDIO_DEVID1 MII_PHYSID1 36 #define MDIO_DEVID2 MII_PHYSID2 37 #define MDIO_SPEED 4 38 #define MDIO_DEVS1 5 39 #define MDIO_DEVS2 6 40 #define MDIO_CTRL2 7 41 #define MDIO_STAT2 8 42 #define MDIO_PMA_TXDIS 9 43 #define MDIO_PMA_RXDET 10 44 #define MDIO_PMA_EXTABLE 11 45 #define MDIO_PKGID1 14 46 #define MDIO_PKGID2 15 47 #define MDIO_AN_ADVERTISE 16 48 #define MDIO_AN_LPA 19 49 #define MDIO_PCS_EEE_ABLE 20 50 #define MDIO_PCS_EEE_ABLE2 21 51 #define MDIO_PMA_NG_EXTABLE 21 52 #define MDIO_PCS_EEE_WK_ERR 22 53 #define MDIO_PHYXS_LNSTAT 24 54 #define MDIO_AN_EEE_ADV 60 55 #define MDIO_AN_EEE_LPABLE 61 56 #define MDIO_AN_EEE_ADV2 62 57 #define MDIO_AN_EEE_LPABLE2 63 58 #define MDIO_PMA_10GBT_SWAPPOL 130 59 #define MDIO_PMA_10GBT_TXPWR 131 60 #define MDIO_PMA_10GBT_SNR 133 61 #define MDIO_PMA_10GBR_FECABLE 170 62 #define MDIO_PCS_10GBX_STAT1 24 63 #define MDIO_PCS_10GBRT_STAT1 32 64 #define MDIO_PCS_10GBRT_STAT2 33 65 #define MDIO_AN_10GBT_CTRL 32 66 #define MDIO_AN_10GBT_STAT 33 67 #define MDIO_PMA_LASI_RXCTRL 0x9000 68 #define MDIO_PMA_LASI_TXCTRL 0x9001 69 #define MDIO_PMA_LASI_CTRL 0x9002 70 #define MDIO_PMA_LASI_RXSTAT 0x9003 71 #define MDIO_PMA_LASI_TXSTAT 0x9004 72 #define MDIO_PMA_LASI_STAT 0x9005 73 #define MDIO_CTRL1_SPEEDSELEXT (BMCR_SPEED1000 | BMCR_SPEED100) 74 #define MDIO_CTRL1_SPEEDSEL (MDIO_CTRL1_SPEEDSELEXT | 0x003c) 75 #define MDIO_CTRL1_FULLDPLX BMCR_FULLDPLX 76 #define MDIO_CTRL1_LPOWER BMCR_PDOWN 77 #define MDIO_CTRL1_RESET BMCR_RESET 78 #define MDIO_PMA_CTRL1_LOOPBACK 0x0001 79 #define MDIO_PMA_CTRL1_SPEED1000 BMCR_SPEED1000 80 #define MDIO_PMA_CTRL1_SPEED100 BMCR_SPEED100 81 #define MDIO_PCS_CTRL1_LOOPBACK BMCR_LOOPBACK 82 #define MDIO_PHYXS_CTRL1_LOOPBACK BMCR_LOOPBACK 83 #define MDIO_AN_CTRL1_RESTART BMCR_ANRESTART 84 #define MDIO_AN_CTRL1_ENABLE BMCR_ANENABLE 85 #define MDIO_AN_CTRL1_XNP 0x2000 86 #define MDIO_PCS_CTRL1_CLKSTOP_EN 0x400 87 #define MDIO_CTRL1_SPEED10G (MDIO_CTRL1_SPEEDSELEXT | 0x00) 88 #define MDIO_CTRL1_SPEED10P2B (MDIO_CTRL1_SPEEDSELEXT | 0x04) 89 #define MDIO_CTRL1_SPEED2_5G (MDIO_CTRL1_SPEEDSELEXT | 0x18) 90 #define MDIO_CTRL1_SPEED5G (MDIO_CTRL1_SPEEDSELEXT | 0x1c) 91 #define MDIO_STAT1_LPOWERABLE 0x0002 92 #define MDIO_STAT1_LSTATUS BMSR_LSTATUS 93 #define MDIO_STAT1_FAULT 0x0080 94 #define MDIO_AN_STAT1_LPABLE 0x0001 95 #define MDIO_AN_STAT1_ABLE BMSR_ANEGCAPABLE 96 #define MDIO_AN_STAT1_RFAULT BMSR_RFAULT 97 #define MDIO_AN_STAT1_COMPLETE BMSR_ANEGCOMPLETE 98 #define MDIO_AN_STAT1_PAGE 0x0040 99 #define MDIO_AN_STAT1_XNP 0x0080 100 #define MDIO_SPEED_10G 0x0001 101 #define MDIO_PMA_SPEED_2B 0x0002 102 #define MDIO_PMA_SPEED_10P 0x0004 103 #define MDIO_PMA_SPEED_1000 0x0010 104 #define MDIO_PMA_SPEED_100 0x0020 105 #define MDIO_PMA_SPEED_10 0x0040 106 #define MDIO_PCS_SPEED_10P2B 0x0002 107 #define MDIO_DEVS_PRESENT(devad) (1 << (devad)) 108 #define MDIO_DEVS_C22PRESENT MDIO_DEVS_PRESENT(0) 109 #define MDIO_DEVS_PMAPMD MDIO_DEVS_PRESENT(MDIO_MMD_PMAPMD) 110 #define MDIO_DEVS_WIS MDIO_DEVS_PRESENT(MDIO_MMD_WIS) 111 #define MDIO_DEVS_PCS MDIO_DEVS_PRESENT(MDIO_MMD_PCS) 112 #define MDIO_DEVS_PHYXS MDIO_DEVS_PRESENT(MDIO_MMD_PHYXS) 113 #define MDIO_DEVS_DTEXS MDIO_DEVS_PRESENT(MDIO_MMD_DTEXS) 114 #define MDIO_DEVS_TC MDIO_DEVS_PRESENT(MDIO_MMD_TC) 115 #define MDIO_DEVS_AN MDIO_DEVS_PRESENT(MDIO_MMD_AN) 116 #define MDIO_DEVS_C22EXT MDIO_DEVS_PRESENT(MDIO_MMD_C22EXT) 117 #define MDIO_DEVS_VEND1 MDIO_DEVS_PRESENT(MDIO_MMD_VEND1) 118 #define MDIO_DEVS_VEND2 MDIO_DEVS_PRESENT(MDIO_MMD_VEND2) 119 #define MDIO_PMA_CTRL2_TYPE 0x000f 120 #define MDIO_PMA_CTRL2_10GBCX4 0x0000 121 #define MDIO_PMA_CTRL2_10GBEW 0x0001 122 #define MDIO_PMA_CTRL2_10GBLW 0x0002 123 #define MDIO_PMA_CTRL2_10GBSW 0x0003 124 #define MDIO_PMA_CTRL2_10GBLX4 0x0004 125 #define MDIO_PMA_CTRL2_10GBER 0x0005 126 #define MDIO_PMA_CTRL2_10GBLR 0x0006 127 #define MDIO_PMA_CTRL2_10GBSR 0x0007 128 #define MDIO_PMA_CTRL2_10GBLRM 0x0008 129 #define MDIO_PMA_CTRL2_10GBT 0x0009 130 #define MDIO_PMA_CTRL2_10GBKX4 0x000a 131 #define MDIO_PMA_CTRL2_10GBKR 0x000b 132 #define MDIO_PMA_CTRL2_1000BT 0x000c 133 #define MDIO_PMA_CTRL2_1000BKX 0x000d 134 #define MDIO_PMA_CTRL2_100BTX 0x000e 135 #define MDIO_PMA_CTRL2_10BT 0x000f 136 #define MDIO_PMA_CTRL2_2_5GBT 0x0030 137 #define MDIO_PMA_CTRL2_5GBT 0x0031 138 #define MDIO_PCS_CTRL2_TYPE 0x0003 139 #define MDIO_PCS_CTRL2_10GBR 0x0000 140 #define MDIO_PCS_CTRL2_10GBX 0x0001 141 #define MDIO_PCS_CTRL2_10GBW 0x0002 142 #define MDIO_PCS_CTRL2_10GBT 0x0003 143 #define MDIO_STAT2_RXFAULT 0x0400 144 #define MDIO_STAT2_TXFAULT 0x0800 145 #define MDIO_STAT2_DEVPRST 0xc000 146 #define MDIO_STAT2_DEVPRST_VAL 0x8000 147 #define MDIO_PMA_STAT2_LBABLE 0x0001 148 #define MDIO_PMA_STAT2_10GBEW 0x0002 149 #define MDIO_PMA_STAT2_10GBLW 0x0004 150 #define MDIO_PMA_STAT2_10GBSW 0x0008 151 #define MDIO_PMA_STAT2_10GBLX4 0x0010 152 #define MDIO_PMA_STAT2_10GBER 0x0020 153 #define MDIO_PMA_STAT2_10GBLR 0x0040 154 #define MDIO_PMA_STAT2_10GBSR 0x0080 155 #define MDIO_PMD_STAT2_TXDISAB 0x0100 156 #define MDIO_PMA_STAT2_EXTABLE 0x0200 157 #define MDIO_PMA_STAT2_RXFLTABLE 0x1000 158 #define MDIO_PMA_STAT2_TXFLTABLE 0x2000 159 #define MDIO_PCS_STAT2_10GBR 0x0001 160 #define MDIO_PCS_STAT2_10GBX 0x0002 161 #define MDIO_PCS_STAT2_10GBW 0x0004 162 #define MDIO_PCS_STAT2_RXFLTABLE 0x1000 163 #define MDIO_PCS_STAT2_TXFLTABLE 0x2000 164 #define MDIO_PMD_TXDIS_GLOBAL 0x0001 165 #define MDIO_PMD_TXDIS_0 0x0002 166 #define MDIO_PMD_TXDIS_1 0x0004 167 #define MDIO_PMD_TXDIS_2 0x0008 168 #define MDIO_PMD_TXDIS_3 0x0010 169 #define MDIO_PMD_RXDET_GLOBAL 0x0001 170 #define MDIO_PMD_RXDET_0 0x0002 171 #define MDIO_PMD_RXDET_1 0x0004 172 #define MDIO_PMD_RXDET_2 0x0008 173 #define MDIO_PMD_RXDET_3 0x0010 174 #define MDIO_PMA_EXTABLE_10GCX4 0x0001 175 #define MDIO_PMA_EXTABLE_10GBLRM 0x0002 176 #define MDIO_PMA_EXTABLE_10GBT 0x0004 177 #define MDIO_PMA_EXTABLE_10GBKX4 0x0008 178 #define MDIO_PMA_EXTABLE_10GBKR 0x0010 179 #define MDIO_PMA_EXTABLE_1000BT 0x0020 180 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 181 #define MDIO_PMA_EXTABLE_100BTX 0x0080 182 #define MDIO_PMA_EXTABLE_10BT 0x0100 183 #define MDIO_PMA_EXTABLE_NBT 0x4000 184 #define MDIO_PHYXS_LNSTAT_SYNC0 0x0001 185 #define MDIO_PHYXS_LNSTAT_SYNC1 0x0002 186 #define MDIO_PHYXS_LNSTAT_SYNC2 0x0004 187 #define MDIO_PHYXS_LNSTAT_SYNC3 0x0008 188 #define MDIO_PHYXS_LNSTAT_ALIGN 0x1000 189 #define MDIO_PMA_10GBT_SWAPPOL_ABNX 0x0001 190 #define MDIO_PMA_10GBT_SWAPPOL_CDNX 0x0002 191 #define MDIO_PMA_10GBT_SWAPPOL_AREV 0x0100 192 #define MDIO_PMA_10GBT_SWAPPOL_BREV 0x0200 193 #define MDIO_PMA_10GBT_SWAPPOL_CREV 0x0400 194 #define MDIO_PMA_10GBT_SWAPPOL_DREV 0x0800 195 #define MDIO_PMA_10GBT_TXPWR_SHORT 0x0001 196 #define MDIO_PMA_10GBT_SNR_BIAS 0x8000 197 #define MDIO_PMA_10GBT_SNR_MAX 127 198 #define MDIO_PMA_10GBR_FECABLE_ABLE 0x0001 199 #define MDIO_PMA_10GBR_FECABLE_ERRABLE 0x0002 200 #define MDIO_PCS_10GBRT_STAT1_BLKLK 0x0001 201 #define MDIO_PCS_10GBRT_STAT2_ERR 0x00ff 202 #define MDIO_PCS_10GBRT_STAT2_BER 0x3f00 203 #define MDIO_AN_10GBT_CTRL_ADV2_5G 0x0080 204 #define MDIO_AN_10GBT_CTRL_ADV5G 0x0100 205 #define MDIO_AN_10GBT_CTRL_ADV10G 0x1000 206 #define MDIO_AN_10GBT_STAT_LP2_5G 0x0020 207 #define MDIO_AN_10GBT_STAT_LP5G 0x0040 208 #define MDIO_AN_10GBT_STAT_LPTRR 0x0200 209 #define MDIO_AN_10GBT_STAT_LPLTABLE 0x0400 210 #define MDIO_AN_10GBT_STAT_LP10G 0x0800 211 #define MDIO_AN_10GBT_STAT_REMOK 0x1000 212 #define MDIO_AN_10GBT_STAT_LOCOK 0x2000 213 #define MDIO_AN_10GBT_STAT_MS 0x4000 214 #define MDIO_AN_10GBT_STAT_MSFLT 0x8000 215 #define MDIO_AN_EEE_ADV_100TX 0x0002 216 #define MDIO_AN_EEE_ADV_1000T 0x0004 217 #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX 218 #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T 219 #define MDIO_EEE_10GT 0x0008 220 #define MDIO_EEE_1000KX 0x0010 221 #define MDIO_EEE_10GKX4 0x0020 222 #define MDIO_EEE_10GKR 0x0040 223 #define MDIO_EEE_40GR_FW 0x0100 224 #define MDIO_EEE_40GR_DS 0x0200 225 #define MDIO_EEE_100GR_FW 0x1000 226 #define MDIO_EEE_100GR_DS 0x2000 227 #define MDIO_EEE_2_5GT 0x0001 228 #define MDIO_EEE_5GT 0x0002 229 #define MDIO_PMA_NG_EXTABLE_2_5GBT 0x0001 230 #define MDIO_PMA_NG_EXTABLE_5GBT 0x0002 231 #define MDIO_PMA_LASI_RX_PHYXSLFLT 0x0001 232 #define MDIO_PMA_LASI_RX_PCSLFLT 0x0008 233 #define MDIO_PMA_LASI_RX_PMALFLT 0x0010 234 #define MDIO_PMA_LASI_RX_OPTICPOWERFLT 0x0020 235 #define MDIO_PMA_LASI_RX_WISLFLT 0x0200 236 #define MDIO_PMA_LASI_TX_PHYXSLFLT 0x0001 237 #define MDIO_PMA_LASI_TX_PCSLFLT 0x0008 238 #define MDIO_PMA_LASI_TX_PMALFLT 0x0010 239 #define MDIO_PMA_LASI_TX_LASERPOWERFLT 0x0080 240 #define MDIO_PMA_LASI_TX_LASERTEMPFLT 0x0100 241 #define MDIO_PMA_LASI_TX_LASERBICURRFLT 0x0200 242 #define MDIO_PMA_LASI_LSALARM 0x0001 243 #define MDIO_PMA_LASI_TXALARM 0x0002 244 #define MDIO_PMA_LASI_RXALARM 0x0004 245 #define MDIO_PHY_ID_C45 0x8000 246 #define MDIO_PHY_ID_PRTAD 0x03e0 247 #define MDIO_PHY_ID_DEVAD 0x001f 248 #define MDIO_PHY_ID_C45_MASK (MDIO_PHY_ID_C45 | MDIO_PHY_ID_PRTAD | MDIO_PHY_ID_DEVAD) 249 #endif 250