1 /**************************************************************************** 2 **************************************************************************** 3 *** 4 *** This header was automatically generated from a Linux kernel header 5 *** of the same name, to make information necessary for userspace to 6 *** call into the kernel available to libc. It contains only constants, 7 *** structures, and macros generated from the original header, and thus, 8 *** contains no copyrightable information. 9 *** 10 *** To edit the content of this header, modify the corresponding 11 *** source file (e.g. under external/kernel-headers/original/) then 12 *** run bionic/libc/kernel/tools/update_all.py 13 *** 14 *** Any manual change here will be lost the next time this script will 15 *** be run. You've been warned! 16 *** 17 **************************************************************************** 18 ****************************************************************************/ 19 #ifndef LINUX_PCI_REGS_H 20 #define LINUX_PCI_REGS_H 21 #define PCI_CFG_SPACE_SIZE 256 22 #define PCI_CFG_SPACE_EXP_SIZE 4096 23 #define PCI_STD_HEADER_SIZEOF 64 24 #define PCI_STD_NUM_BARS 6 25 #define PCI_VENDOR_ID 0x00 26 #define PCI_DEVICE_ID 0x02 27 #define PCI_COMMAND 0x04 28 #define PCI_COMMAND_IO 0x1 29 #define PCI_COMMAND_MEMORY 0x2 30 #define PCI_COMMAND_MASTER 0x4 31 #define PCI_COMMAND_SPECIAL 0x8 32 #define PCI_COMMAND_INVALIDATE 0x10 33 #define PCI_COMMAND_VGA_PALETTE 0x20 34 #define PCI_COMMAND_PARITY 0x40 35 #define PCI_COMMAND_WAIT 0x80 36 #define PCI_COMMAND_SERR 0x100 37 #define PCI_COMMAND_FAST_BACK 0x200 38 #define PCI_COMMAND_INTX_DISABLE 0x400 39 #define PCI_STATUS 0x06 40 #define PCI_STATUS_IMM_READY 0x01 41 #define PCI_STATUS_INTERRUPT 0x08 42 #define PCI_STATUS_CAP_LIST 0x10 43 #define PCI_STATUS_66MHZ 0x20 44 #define PCI_STATUS_UDF 0x40 45 #define PCI_STATUS_FAST_BACK 0x80 46 #define PCI_STATUS_PARITY 0x100 47 #define PCI_STATUS_DEVSEL_MASK 0x600 48 #define PCI_STATUS_DEVSEL_FAST 0x000 49 #define PCI_STATUS_DEVSEL_MEDIUM 0x200 50 #define PCI_STATUS_DEVSEL_SLOW 0x400 51 #define PCI_STATUS_SIG_TARGET_ABORT 0x800 52 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 53 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 54 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 55 #define PCI_STATUS_DETECTED_PARITY 0x8000 56 #define PCI_CLASS_REVISION 0x08 57 #define PCI_REVISION_ID 0x08 58 #define PCI_CLASS_PROG 0x09 59 #define PCI_CLASS_DEVICE 0x0a 60 #define PCI_CACHE_LINE_SIZE 0x0c 61 #define PCI_LATENCY_TIMER 0x0d 62 #define PCI_HEADER_TYPE 0x0e 63 #define PCI_HEADER_TYPE_NORMAL 0 64 #define PCI_HEADER_TYPE_BRIDGE 1 65 #define PCI_HEADER_TYPE_CARDBUS 2 66 #define PCI_BIST 0x0f 67 #define PCI_BIST_CODE_MASK 0x0f 68 #define PCI_BIST_START 0x40 69 #define PCI_BIST_CAPABLE 0x80 70 #define PCI_BASE_ADDRESS_0 0x10 71 #define PCI_BASE_ADDRESS_1 0x14 72 #define PCI_BASE_ADDRESS_2 0x18 73 #define PCI_BASE_ADDRESS_3 0x1c 74 #define PCI_BASE_ADDRESS_4 0x20 75 #define PCI_BASE_ADDRESS_5 0x24 76 #define PCI_BASE_ADDRESS_SPACE 0x01 77 #define PCI_BASE_ADDRESS_SPACE_IO 0x01 78 #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00 79 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06 80 #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 81 #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 82 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 83 #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 84 #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL) 85 #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL) 86 #define PCI_CARDBUS_CIS 0x28 87 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c 88 #define PCI_SUBSYSTEM_ID 0x2e 89 #define PCI_ROM_ADDRESS 0x30 90 #define PCI_ROM_ADDRESS_ENABLE 0x01 91 #define PCI_ROM_ADDRESS_MASK (~0x7ffU) 92 #define PCI_CAPABILITY_LIST 0x34 93 #define PCI_INTERRUPT_LINE 0x3c 94 #define PCI_INTERRUPT_PIN 0x3d 95 #define PCI_MIN_GNT 0x3e 96 #define PCI_MAX_LAT 0x3f 97 #define PCI_PRIMARY_BUS 0x18 98 #define PCI_SECONDARY_BUS 0x19 99 #define PCI_SUBORDINATE_BUS 0x1a 100 #define PCI_SEC_LATENCY_TIMER 0x1b 101 #define PCI_IO_BASE 0x1c 102 #define PCI_IO_LIMIT 0x1d 103 #define PCI_IO_RANGE_TYPE_MASK 0x0fUL 104 #define PCI_IO_RANGE_TYPE_16 0x00 105 #define PCI_IO_RANGE_TYPE_32 0x01 106 #define PCI_IO_RANGE_MASK (~0x0fUL) 107 #define PCI_IO_1K_RANGE_MASK (~0x03UL) 108 #define PCI_SEC_STATUS 0x1e 109 #define PCI_MEMORY_BASE 0x20 110 #define PCI_MEMORY_LIMIT 0x22 111 #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL 112 #define PCI_MEMORY_RANGE_MASK (~0x0fUL) 113 #define PCI_PREF_MEMORY_BASE 0x24 114 #define PCI_PREF_MEMORY_LIMIT 0x26 115 #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL 116 #define PCI_PREF_RANGE_TYPE_32 0x00 117 #define PCI_PREF_RANGE_TYPE_64 0x01 118 #define PCI_PREF_RANGE_MASK (~0x0fUL) 119 #define PCI_PREF_BASE_UPPER32 0x28 120 #define PCI_PREF_LIMIT_UPPER32 0x2c 121 #define PCI_IO_BASE_UPPER16 0x30 122 #define PCI_IO_LIMIT_UPPER16 0x32 123 #define PCI_ROM_ADDRESS1 0x38 124 #define PCI_BRIDGE_CONTROL 0x3e 125 #define PCI_BRIDGE_CTL_PARITY 0x01 126 #define PCI_BRIDGE_CTL_SERR 0x02 127 #define PCI_BRIDGE_CTL_ISA 0x04 128 #define PCI_BRIDGE_CTL_VGA 0x08 129 #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 130 #define PCI_BRIDGE_CTL_BUS_RESET 0x40 131 #define PCI_BRIDGE_CTL_FAST_BACK 0x80 132 #define PCI_CB_CAPABILITY_LIST 0x14 133 #define PCI_CB_SEC_STATUS 0x16 134 #define PCI_CB_PRIMARY_BUS 0x18 135 #define PCI_CB_CARD_BUS 0x19 136 #define PCI_CB_SUBORDINATE_BUS 0x1a 137 #define PCI_CB_LATENCY_TIMER 0x1b 138 #define PCI_CB_MEMORY_BASE_0 0x1c 139 #define PCI_CB_MEMORY_LIMIT_0 0x20 140 #define PCI_CB_MEMORY_BASE_1 0x24 141 #define PCI_CB_MEMORY_LIMIT_1 0x28 142 #define PCI_CB_IO_BASE_0 0x2c 143 #define PCI_CB_IO_BASE_0_HI 0x2e 144 #define PCI_CB_IO_LIMIT_0 0x30 145 #define PCI_CB_IO_LIMIT_0_HI 0x32 146 #define PCI_CB_IO_BASE_1 0x34 147 #define PCI_CB_IO_BASE_1_HI 0x36 148 #define PCI_CB_IO_LIMIT_1 0x38 149 #define PCI_CB_IO_LIMIT_1_HI 0x3a 150 #define PCI_CB_IO_RANGE_MASK (~0x03UL) 151 #define PCI_CB_BRIDGE_CONTROL 0x3e 152 #define PCI_CB_BRIDGE_CTL_PARITY 0x01 153 #define PCI_CB_BRIDGE_CTL_SERR 0x02 154 #define PCI_CB_BRIDGE_CTL_ISA 0x04 155 #define PCI_CB_BRIDGE_CTL_VGA 0x08 156 #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20 157 #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 158 #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 159 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 160 #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200 161 #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400 162 #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40 163 #define PCI_CB_SUBSYSTEM_ID 0x42 164 #define PCI_CB_LEGACY_MODE_BASE 0x44 165 #define PCI_CAP_LIST_ID 0 166 #define PCI_CAP_ID_PM 0x01 167 #define PCI_CAP_ID_AGP 0x02 168 #define PCI_CAP_ID_VPD 0x03 169 #define PCI_CAP_ID_SLOTID 0x04 170 #define PCI_CAP_ID_MSI 0x05 171 #define PCI_CAP_ID_CHSWP 0x06 172 #define PCI_CAP_ID_PCIX 0x07 173 #define PCI_CAP_ID_HT 0x08 174 #define PCI_CAP_ID_VNDR 0x09 175 #define PCI_CAP_ID_DBG 0x0A 176 #define PCI_CAP_ID_CCRC 0x0B 177 #define PCI_CAP_ID_SHPC 0x0C 178 #define PCI_CAP_ID_SSVID 0x0D 179 #define PCI_CAP_ID_AGP3 0x0E 180 #define PCI_CAP_ID_SECDEV 0x0F 181 #define PCI_CAP_ID_EXP 0x10 182 #define PCI_CAP_ID_MSIX 0x11 183 #define PCI_CAP_ID_SATA 0x12 184 #define PCI_CAP_ID_AF 0x13 185 #define PCI_CAP_ID_EA 0x14 186 #define PCI_CAP_ID_MAX PCI_CAP_ID_EA 187 #define PCI_CAP_LIST_NEXT 1 188 #define PCI_CAP_FLAGS 2 189 #define PCI_CAP_SIZEOF 4 190 #define PCI_PM_PMC 2 191 #define PCI_PM_CAP_VER_MASK 0x0007 192 #define PCI_PM_CAP_PME_CLOCK 0x0008 193 #define PCI_PM_CAP_RESERVED 0x0010 194 #define PCI_PM_CAP_DSI 0x0020 195 #define PCI_PM_CAP_AUX_POWER 0x01C0 196 #define PCI_PM_CAP_D1 0x0200 197 #define PCI_PM_CAP_D2 0x0400 198 #define PCI_PM_CAP_PME 0x0800 199 #define PCI_PM_CAP_PME_MASK 0xF800 200 #define PCI_PM_CAP_PME_D0 0x0800 201 #define PCI_PM_CAP_PME_D1 0x1000 202 #define PCI_PM_CAP_PME_D2 0x2000 203 #define PCI_PM_CAP_PME_D3 0x4000 204 #define PCI_PM_CAP_PME_D3cold 0x8000 205 #define PCI_PM_CAP_PME_SHIFT 11 206 #define PCI_PM_CTRL 4 207 #define PCI_PM_CTRL_STATE_MASK 0x0003 208 #define PCI_PM_CTRL_NO_SOFT_RESET 0x0008 209 #define PCI_PM_CTRL_PME_ENABLE 0x0100 210 #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 211 #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 212 #define PCI_PM_CTRL_PME_STATUS 0x8000 213 #define PCI_PM_PPB_EXTENSIONS 6 214 #define PCI_PM_PPB_B2_B3 0x40 215 #define PCI_PM_BPCC_ENABLE 0x80 216 #define PCI_PM_DATA_REGISTER 7 217 #define PCI_PM_SIZEOF 8 218 #define PCI_AGP_VERSION 2 219 #define PCI_AGP_RFU 3 220 #define PCI_AGP_STATUS 4 221 #define PCI_AGP_STATUS_RQ_MASK 0xff000000 222 #define PCI_AGP_STATUS_SBA 0x0200 223 #define PCI_AGP_STATUS_64BIT 0x0020 224 #define PCI_AGP_STATUS_FW 0x0010 225 #define PCI_AGP_STATUS_RATE4 0x0004 226 #define PCI_AGP_STATUS_RATE2 0x0002 227 #define PCI_AGP_STATUS_RATE1 0x0001 228 #define PCI_AGP_COMMAND 8 229 #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 230 #define PCI_AGP_COMMAND_SBA 0x0200 231 #define PCI_AGP_COMMAND_AGP 0x0100 232 #define PCI_AGP_COMMAND_64BIT 0x0020 233 #define PCI_AGP_COMMAND_FW 0x0010 234 #define PCI_AGP_COMMAND_RATE4 0x0004 235 #define PCI_AGP_COMMAND_RATE2 0x0002 236 #define PCI_AGP_COMMAND_RATE1 0x0001 237 #define PCI_AGP_SIZEOF 12 238 #define PCI_VPD_ADDR 2 239 #define PCI_VPD_ADDR_MASK 0x7fff 240 #define PCI_VPD_ADDR_F 0x8000 241 #define PCI_VPD_DATA 4 242 #define PCI_CAP_VPD_SIZEOF 8 243 #define PCI_SID_ESR 2 244 #define PCI_SID_ESR_NSLOTS 0x1f 245 #define PCI_SID_ESR_FIC 0x20 246 #define PCI_SID_CHASSIS_NR 3 247 #define PCI_MSI_FLAGS 2 248 #define PCI_MSI_FLAGS_ENABLE 0x0001 249 #define PCI_MSI_FLAGS_QMASK 0x000e 250 #define PCI_MSI_FLAGS_QSIZE 0x0070 251 #define PCI_MSI_FLAGS_64BIT 0x0080 252 #define PCI_MSI_FLAGS_MASKBIT 0x0100 253 #define PCI_MSI_RFU 3 254 #define PCI_MSI_ADDRESS_LO 4 255 #define PCI_MSI_ADDRESS_HI 8 256 #define PCI_MSI_DATA_32 8 257 #define PCI_MSI_MASK_32 12 258 #define PCI_MSI_PENDING_32 16 259 #define PCI_MSI_DATA_64 12 260 #define PCI_MSI_MASK_64 16 261 #define PCI_MSI_PENDING_64 20 262 #define PCI_MSIX_FLAGS 2 263 #define PCI_MSIX_FLAGS_QSIZE 0x07FF 264 #define PCI_MSIX_FLAGS_MASKALL 0x4000 265 #define PCI_MSIX_FLAGS_ENABLE 0x8000 266 #define PCI_MSIX_TABLE 4 267 #define PCI_MSIX_TABLE_BIR 0x00000007 268 #define PCI_MSIX_TABLE_OFFSET 0xfffffff8 269 #define PCI_MSIX_PBA 8 270 #define PCI_MSIX_PBA_BIR 0x00000007 271 #define PCI_MSIX_PBA_OFFSET 0xfffffff8 272 #define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR 273 #define PCI_CAP_MSIX_SIZEOF 12 274 #define PCI_MSIX_ENTRY_SIZE 16 275 #define PCI_MSIX_ENTRY_LOWER_ADDR 0 276 #define PCI_MSIX_ENTRY_UPPER_ADDR 4 277 #define PCI_MSIX_ENTRY_DATA 8 278 #define PCI_MSIX_ENTRY_VECTOR_CTRL 12 279 #define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001 280 #define PCI_CHSWP_CSR 2 281 #define PCI_CHSWP_DHA 0x01 282 #define PCI_CHSWP_EIM 0x02 283 #define PCI_CHSWP_PIE 0x04 284 #define PCI_CHSWP_LOO 0x08 285 #define PCI_CHSWP_PI 0x30 286 #define PCI_CHSWP_EXT 0x40 287 #define PCI_CHSWP_INS 0x80 288 #define PCI_AF_LENGTH 2 289 #define PCI_AF_CAP 3 290 #define PCI_AF_CAP_TP 0x01 291 #define PCI_AF_CAP_FLR 0x02 292 #define PCI_AF_CTRL 4 293 #define PCI_AF_CTRL_FLR 0x01 294 #define PCI_AF_STATUS 5 295 #define PCI_AF_STATUS_TP 0x01 296 #define PCI_CAP_AF_SIZEOF 6 297 #define PCI_EA_NUM_ENT 2 298 #define PCI_EA_NUM_ENT_MASK 0x3f 299 #define PCI_EA_FIRST_ENT 4 300 #define PCI_EA_FIRST_ENT_BRIDGE 8 301 #define PCI_EA_ES 0x00000007 302 #define PCI_EA_BEI 0x000000f0 303 #define PCI_EA_SEC_BUS_MASK 0xff 304 #define PCI_EA_SUB_BUS_MASK 0xff00 305 #define PCI_EA_SUB_BUS_SHIFT 8 306 #define PCI_EA_BEI_BAR0 0 307 #define PCI_EA_BEI_BAR5 5 308 #define PCI_EA_BEI_BRIDGE 6 309 #define PCI_EA_BEI_ENI 7 310 #define PCI_EA_BEI_ROM 8 311 #define PCI_EA_BEI_VF_BAR0 9 312 #define PCI_EA_BEI_VF_BAR5 14 313 #define PCI_EA_BEI_RESERVED 15 314 #define PCI_EA_PP 0x0000ff00 315 #define PCI_EA_SP 0x00ff0000 316 #define PCI_EA_P_MEM 0x00 317 #define PCI_EA_P_MEM_PREFETCH 0x01 318 #define PCI_EA_P_IO 0x02 319 #define PCI_EA_P_VF_MEM_PREFETCH 0x03 320 #define PCI_EA_P_VF_MEM 0x04 321 #define PCI_EA_P_BRIDGE_MEM 0x05 322 #define PCI_EA_P_BRIDGE_MEM_PREFETCH 0x06 323 #define PCI_EA_P_BRIDGE_IO 0x07 324 #define PCI_EA_P_MEM_RESERVED 0xfd 325 #define PCI_EA_P_IO_RESERVED 0xfe 326 #define PCI_EA_P_UNAVAILABLE 0xff 327 #define PCI_EA_WRITABLE 0x40000000 328 #define PCI_EA_ENABLE 0x80000000 329 #define PCI_EA_BASE 4 330 #define PCI_EA_MAX_OFFSET 8 331 #define PCI_EA_IS_64 0x00000002 332 #define PCI_EA_FIELD_MASK 0xfffffffc 333 #define PCI_X_CMD 2 334 #define PCI_X_CMD_DPERR_E 0x0001 335 #define PCI_X_CMD_ERO 0x0002 336 #define PCI_X_CMD_READ_512 0x0000 337 #define PCI_X_CMD_READ_1K 0x0004 338 #define PCI_X_CMD_READ_2K 0x0008 339 #define PCI_X_CMD_READ_4K 0x000c 340 #define PCI_X_CMD_MAX_READ 0x000c 341 #define PCI_X_CMD_SPLIT_1 0x0000 342 #define PCI_X_CMD_SPLIT_2 0x0010 343 #define PCI_X_CMD_SPLIT_3 0x0020 344 #define PCI_X_CMD_SPLIT_4 0x0030 345 #define PCI_X_CMD_SPLIT_8 0x0040 346 #define PCI_X_CMD_SPLIT_12 0x0050 347 #define PCI_X_CMD_SPLIT_16 0x0060 348 #define PCI_X_CMD_SPLIT_32 0x0070 349 #define PCI_X_CMD_MAX_SPLIT 0x0070 350 #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) 351 #define PCI_X_STATUS 4 352 #define PCI_X_STATUS_DEVFN 0x000000ff 353 #define PCI_X_STATUS_BUS 0x0000ff00 354 #define PCI_X_STATUS_64BIT 0x00010000 355 #define PCI_X_STATUS_133MHZ 0x00020000 356 #define PCI_X_STATUS_SPL_DISC 0x00040000 357 #define PCI_X_STATUS_UNX_SPL 0x00080000 358 #define PCI_X_STATUS_COMPLEX 0x00100000 359 #define PCI_X_STATUS_MAX_READ 0x00600000 360 #define PCI_X_STATUS_MAX_SPLIT 0x03800000 361 #define PCI_X_STATUS_MAX_CUM 0x1c000000 362 #define PCI_X_STATUS_SPL_ERR 0x20000000 363 #define PCI_X_STATUS_266MHZ 0x40000000 364 #define PCI_X_STATUS_533MHZ 0x80000000 365 #define PCI_X_ECC_CSR 8 366 #define PCI_CAP_PCIX_SIZEOF_V0 8 367 #define PCI_CAP_PCIX_SIZEOF_V1 24 368 #define PCI_CAP_PCIX_SIZEOF_V2 PCI_CAP_PCIX_SIZEOF_V1 369 #define PCI_X_BRIDGE_SSTATUS 2 370 #define PCI_X_SSTATUS_64BIT 0x0001 371 #define PCI_X_SSTATUS_133MHZ 0x0002 372 #define PCI_X_SSTATUS_FREQ 0x03c0 373 #define PCI_X_SSTATUS_VERS 0x3000 374 #define PCI_X_SSTATUS_V1 0x1000 375 #define PCI_X_SSTATUS_V2 0x2000 376 #define PCI_X_SSTATUS_266MHZ 0x4000 377 #define PCI_X_SSTATUS_533MHZ 0x8000 378 #define PCI_X_BRIDGE_STATUS 4 379 #define PCI_SSVID_VENDOR_ID 4 380 #define PCI_SSVID_DEVICE_ID 6 381 #define PCI_EXP_FLAGS 2 382 #define PCI_EXP_FLAGS_VERS 0x000f 383 #define PCI_EXP_FLAGS_TYPE 0x00f0 384 #define PCI_EXP_TYPE_ENDPOINT 0x0 385 #define PCI_EXP_TYPE_LEG_END 0x1 386 #define PCI_EXP_TYPE_ROOT_PORT 0x4 387 #define PCI_EXP_TYPE_UPSTREAM 0x5 388 #define PCI_EXP_TYPE_DOWNSTREAM 0x6 389 #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 390 #define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 391 #define PCI_EXP_TYPE_RC_END 0x9 392 #define PCI_EXP_TYPE_RC_EC 0xa 393 #define PCI_EXP_FLAGS_SLOT 0x0100 394 #define PCI_EXP_FLAGS_IRQ 0x3e00 395 #define PCI_EXP_DEVCAP 4 396 #define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 397 #define PCI_EXP_DEVCAP_PHANTOM 0x00000018 398 #define PCI_EXP_DEVCAP_EXT_TAG 0x00000020 399 #define PCI_EXP_DEVCAP_L0S 0x000001c0 400 #define PCI_EXP_DEVCAP_L1 0x00000e00 401 #define PCI_EXP_DEVCAP_ATN_BUT 0x00001000 402 #define PCI_EXP_DEVCAP_ATN_IND 0x00002000 403 #define PCI_EXP_DEVCAP_PWR_IND 0x00004000 404 #define PCI_EXP_DEVCAP_RBER 0x00008000 405 #define PCI_EXP_DEVCAP_PWR_VAL 0x03fc0000 406 #define PCI_EXP_DEVCAP_PWR_SCL 0x0c000000 407 #define PCI_EXP_DEVCAP_FLR 0x10000000 408 #define PCI_EXP_DEVCTL 8 409 #define PCI_EXP_DEVCTL_CERE 0x0001 410 #define PCI_EXP_DEVCTL_NFERE 0x0002 411 #define PCI_EXP_DEVCTL_FERE 0x0004 412 #define PCI_EXP_DEVCTL_URRE 0x0008 413 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 414 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 415 #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 416 #define PCI_EXP_DEVCTL_PHANTOM 0x0200 417 #define PCI_EXP_DEVCTL_AUX_PME 0x0400 418 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 419 #define PCI_EXP_DEVCTL_READRQ 0x7000 420 #define PCI_EXP_DEVCTL_READRQ_128B 0x0000 421 #define PCI_EXP_DEVCTL_READRQ_256B 0x1000 422 #define PCI_EXP_DEVCTL_READRQ_512B 0x2000 423 #define PCI_EXP_DEVCTL_READRQ_1024B 0x3000 424 #define PCI_EXP_DEVCTL_READRQ_2048B 0x4000 425 #define PCI_EXP_DEVCTL_READRQ_4096B 0x5000 426 #define PCI_EXP_DEVCTL_BCR_FLR 0x8000 427 #define PCI_EXP_DEVSTA 10 428 #define PCI_EXP_DEVSTA_CED 0x0001 429 #define PCI_EXP_DEVSTA_NFED 0x0002 430 #define PCI_EXP_DEVSTA_FED 0x0004 431 #define PCI_EXP_DEVSTA_URD 0x0008 432 #define PCI_EXP_DEVSTA_AUXPD 0x0010 433 #define PCI_EXP_DEVSTA_TRPND 0x0020 434 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V1 12 435 #define PCI_EXP_LNKCAP 12 436 #define PCI_EXP_LNKCAP_SLS 0x0000000f 437 #define PCI_EXP_LNKCAP_SLS_2_5GB 0x00000001 438 #define PCI_EXP_LNKCAP_SLS_5_0GB 0x00000002 439 #define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 440 #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 441 #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 442 #define PCI_EXP_LNKCAP_MLW 0x000003f0 443 #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 444 #define PCI_EXP_LNKCAP_L0SEL 0x00007000 445 #define PCI_EXP_LNKCAP_L1EL 0x00038000 446 #define PCI_EXP_LNKCAP_CLKPM 0x00040000 447 #define PCI_EXP_LNKCAP_SDERC 0x00080000 448 #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 449 #define PCI_EXP_LNKCAP_LBNC 0x00200000 450 #define PCI_EXP_LNKCAP_PN 0xff000000 451 #define PCI_EXP_LNKCTL 16 452 #define PCI_EXP_LNKCTL_ASPMC 0x0003 453 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 454 #define PCI_EXP_LNKCTL_ASPM_L1 0x0002 455 #define PCI_EXP_LNKCTL_RCB 0x0008 456 #define PCI_EXP_LNKCTL_LD 0x0010 457 #define PCI_EXP_LNKCTL_RL 0x0020 458 #define PCI_EXP_LNKCTL_CCC 0x0040 459 #define PCI_EXP_LNKCTL_ES 0x0080 460 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x0100 461 #define PCI_EXP_LNKCTL_HAWD 0x0200 462 #define PCI_EXP_LNKCTL_LBMIE 0x0400 463 #define PCI_EXP_LNKCTL_LABIE 0x0800 464 #define PCI_EXP_LNKSTA 18 465 #define PCI_EXP_LNKSTA_CLS 0x000f 466 #define PCI_EXP_LNKSTA_CLS_2_5GB 0x0001 467 #define PCI_EXP_LNKSTA_CLS_5_0GB 0x0002 468 #define PCI_EXP_LNKSTA_CLS_8_0GB 0x0003 469 #define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 470 #define PCI_EXP_LNKSTA_CLS_32_0GB 0x0005 471 #define PCI_EXP_LNKSTA_NLW 0x03f0 472 #define PCI_EXP_LNKSTA_NLW_X1 0x0010 473 #define PCI_EXP_LNKSTA_NLW_X2 0x0020 474 #define PCI_EXP_LNKSTA_NLW_X4 0x0040 475 #define PCI_EXP_LNKSTA_NLW_X8 0x0080 476 #define PCI_EXP_LNKSTA_NLW_SHIFT 4 477 #define PCI_EXP_LNKSTA_LT 0x0800 478 #define PCI_EXP_LNKSTA_SLC 0x1000 479 #define PCI_EXP_LNKSTA_DLLLA 0x2000 480 #define PCI_EXP_LNKSTA_LBMS 0x4000 481 #define PCI_EXP_LNKSTA_LABS 0x8000 482 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V1 20 483 #define PCI_EXP_SLTCAP 20 484 #define PCI_EXP_SLTCAP_ABP 0x00000001 485 #define PCI_EXP_SLTCAP_PCP 0x00000002 486 #define PCI_EXP_SLTCAP_MRLSP 0x00000004 487 #define PCI_EXP_SLTCAP_AIP 0x00000008 488 #define PCI_EXP_SLTCAP_PIP 0x00000010 489 #define PCI_EXP_SLTCAP_HPS 0x00000020 490 #define PCI_EXP_SLTCAP_HPC 0x00000040 491 #define PCI_EXP_SLTCAP_SPLV 0x00007f80 492 #define PCI_EXP_SLTCAP_SPLS 0x00018000 493 #define PCI_EXP_SLTCAP_EIP 0x00020000 494 #define PCI_EXP_SLTCAP_NCCS 0x00040000 495 #define PCI_EXP_SLTCAP_PSN 0xfff80000 496 #define PCI_EXP_SLTCTL 24 497 #define PCI_EXP_SLTCTL_ABPE 0x0001 498 #define PCI_EXP_SLTCTL_PFDE 0x0002 499 #define PCI_EXP_SLTCTL_MRLSCE 0x0004 500 #define PCI_EXP_SLTCTL_PDCE 0x0008 501 #define PCI_EXP_SLTCTL_CCIE 0x0010 502 #define PCI_EXP_SLTCTL_HPIE 0x0020 503 #define PCI_EXP_SLTCTL_AIC 0x00c0 504 #define PCI_EXP_SLTCTL_ATTN_IND_SHIFT 6 505 #define PCI_EXP_SLTCTL_ATTN_IND_ON 0x0040 506 #define PCI_EXP_SLTCTL_ATTN_IND_BLINK 0x0080 507 #define PCI_EXP_SLTCTL_ATTN_IND_OFF 0x00c0 508 #define PCI_EXP_SLTCTL_PIC 0x0300 509 #define PCI_EXP_SLTCTL_PWR_IND_ON 0x0100 510 #define PCI_EXP_SLTCTL_PWR_IND_BLINK 0x0200 511 #define PCI_EXP_SLTCTL_PWR_IND_OFF 0x0300 512 #define PCI_EXP_SLTCTL_PCC 0x0400 513 #define PCI_EXP_SLTCTL_PWR_ON 0x0000 514 #define PCI_EXP_SLTCTL_PWR_OFF 0x0400 515 #define PCI_EXP_SLTCTL_EIC 0x0800 516 #define PCI_EXP_SLTCTL_DLLSCE 0x1000 517 #define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 518 #define PCI_EXP_SLTSTA 26 519 #define PCI_EXP_SLTSTA_ABP 0x0001 520 #define PCI_EXP_SLTSTA_PFD 0x0002 521 #define PCI_EXP_SLTSTA_MRLSC 0x0004 522 #define PCI_EXP_SLTSTA_PDC 0x0008 523 #define PCI_EXP_SLTSTA_CC 0x0010 524 #define PCI_EXP_SLTSTA_MRLSS 0x0020 525 #define PCI_EXP_SLTSTA_PDS 0x0040 526 #define PCI_EXP_SLTSTA_EIS 0x0080 527 #define PCI_EXP_SLTSTA_DLLSC 0x0100 528 #define PCI_EXP_RTCTL 28 529 #define PCI_EXP_RTCTL_SECEE 0x0001 530 #define PCI_EXP_RTCTL_SENFEE 0x0002 531 #define PCI_EXP_RTCTL_SEFEE 0x0004 532 #define PCI_EXP_RTCTL_PMEIE 0x0008 533 #define PCI_EXP_RTCTL_CRSSVE 0x0010 534 #define PCI_EXP_RTCAP 30 535 #define PCI_EXP_RTCAP_CRSVIS 0x0001 536 #define PCI_EXP_RTSTA 32 537 #define PCI_EXP_RTSTA_PME 0x00010000 538 #define PCI_EXP_RTSTA_PENDING 0x00020000 539 #define PCI_EXP_DEVCAP2 36 540 #define PCI_EXP_DEVCAP2_COMP_TMOUT_DIS 0x00000010 541 #define PCI_EXP_DEVCAP2_ARI 0x00000020 542 #define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 543 #define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 544 #define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 545 #define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 546 #define PCI_EXP_DEVCAP2_LTR 0x00000800 547 #define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 548 #define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 549 #define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 550 #define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 551 #define PCI_EXP_DEVCTL2 40 552 #define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f 553 #define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 554 #define PCI_EXP_DEVCTL2_ARI 0x0020 555 #define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 556 #define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 557 #define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 558 #define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 559 #define PCI_EXP_DEVCTL2_LTR_EN 0x0400 560 #define PCI_EXP_DEVCTL2_OBFF_MSGA_EN 0x2000 561 #define PCI_EXP_DEVCTL2_OBFF_MSGB_EN 0x4000 562 #define PCI_EXP_DEVCTL2_OBFF_WAKE_EN 0x6000 563 #define PCI_EXP_DEVSTA2 42 564 #define PCI_CAP_EXP_RC_ENDPOINT_SIZEOF_V2 44 565 #define PCI_EXP_LNKCAP2 44 566 #define PCI_EXP_LNKCAP2_SLS_2_5GB 0x00000002 567 #define PCI_EXP_LNKCAP2_SLS_5_0GB 0x00000004 568 #define PCI_EXP_LNKCAP2_SLS_8_0GB 0x00000008 569 #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 570 #define PCI_EXP_LNKCAP2_SLS_32_0GB 0x00000020 571 #define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 572 #define PCI_EXP_LNKCTL2 48 573 #define PCI_EXP_LNKCTL2_TLS 0x000f 574 #define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 575 #define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 576 #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 577 #define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 578 #define PCI_EXP_LNKCTL2_TLS_32_0GT 0x0005 579 #define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 580 #define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 581 #define PCI_EXP_LNKCTL2_HASD 0x0020 582 #define PCI_EXP_LNKSTA2 50 583 #define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 584 #define PCI_EXP_SLTCAP2 52 585 #define PCI_EXP_SLTCAP2_IBPD 0x00000001 586 #define PCI_EXP_SLTCTL2 56 587 #define PCI_EXP_SLTSTA2 58 588 #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) 589 #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf) 590 #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc) 591 #define PCI_EXT_CAP_ID_ERR 0x01 592 #define PCI_EXT_CAP_ID_VC 0x02 593 #define PCI_EXT_CAP_ID_DSN 0x03 594 #define PCI_EXT_CAP_ID_PWR 0x04 595 #define PCI_EXT_CAP_ID_RCLD 0x05 596 #define PCI_EXT_CAP_ID_RCILC 0x06 597 #define PCI_EXT_CAP_ID_RCEC 0x07 598 #define PCI_EXT_CAP_ID_MFVC 0x08 599 #define PCI_EXT_CAP_ID_VC9 0x09 600 #define PCI_EXT_CAP_ID_RCRB 0x0A 601 #define PCI_EXT_CAP_ID_VNDR 0x0B 602 #define PCI_EXT_CAP_ID_CAC 0x0C 603 #define PCI_EXT_CAP_ID_ACS 0x0D 604 #define PCI_EXT_CAP_ID_ARI 0x0E 605 #define PCI_EXT_CAP_ID_ATS 0x0F 606 #define PCI_EXT_CAP_ID_SRIOV 0x10 607 #define PCI_EXT_CAP_ID_MRIOV 0x11 608 #define PCI_EXT_CAP_ID_MCAST 0x12 609 #define PCI_EXT_CAP_ID_PRI 0x13 610 #define PCI_EXT_CAP_ID_AMD_XXX 0x14 611 #define PCI_EXT_CAP_ID_REBAR 0x15 612 #define PCI_EXT_CAP_ID_DPA 0x16 613 #define PCI_EXT_CAP_ID_TPH 0x17 614 #define PCI_EXT_CAP_ID_LTR 0x18 615 #define PCI_EXT_CAP_ID_SECPCI 0x19 616 #define PCI_EXT_CAP_ID_PMUX 0x1A 617 #define PCI_EXT_CAP_ID_PASID 0x1B 618 #define PCI_EXT_CAP_ID_DPC 0x1D 619 #define PCI_EXT_CAP_ID_L1SS 0x1E 620 #define PCI_EXT_CAP_ID_PTM 0x1F 621 #define PCI_EXT_CAP_ID_DLF 0x25 622 #define PCI_EXT_CAP_ID_PL_16GT 0x26 623 #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT 624 #define PCI_EXT_CAP_DSN_SIZEOF 12 625 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 626 #define PCI_ERR_UNCOR_STATUS 4 627 #define PCI_ERR_UNC_UND 0x00000001 628 #define PCI_ERR_UNC_DLP 0x00000010 629 #define PCI_ERR_UNC_SURPDN 0x00000020 630 #define PCI_ERR_UNC_POISON_TLP 0x00001000 631 #define PCI_ERR_UNC_FCP 0x00002000 632 #define PCI_ERR_UNC_COMP_TIME 0x00004000 633 #define PCI_ERR_UNC_COMP_ABORT 0x00008000 634 #define PCI_ERR_UNC_UNX_COMP 0x00010000 635 #define PCI_ERR_UNC_RX_OVER 0x00020000 636 #define PCI_ERR_UNC_MALF_TLP 0x00040000 637 #define PCI_ERR_UNC_ECRC 0x00080000 638 #define PCI_ERR_UNC_UNSUP 0x00100000 639 #define PCI_ERR_UNC_ACSV 0x00200000 640 #define PCI_ERR_UNC_INTN 0x00400000 641 #define PCI_ERR_UNC_MCBTLP 0x00800000 642 #define PCI_ERR_UNC_ATOMEG 0x01000000 643 #define PCI_ERR_UNC_TLPPRE 0x02000000 644 #define PCI_ERR_UNCOR_MASK 8 645 #define PCI_ERR_UNCOR_SEVER 12 646 #define PCI_ERR_COR_STATUS 16 647 #define PCI_ERR_COR_RCVR 0x00000001 648 #define PCI_ERR_COR_BAD_TLP 0x00000040 649 #define PCI_ERR_COR_BAD_DLLP 0x00000080 650 #define PCI_ERR_COR_REP_ROLL 0x00000100 651 #define PCI_ERR_COR_REP_TIMER 0x00001000 652 #define PCI_ERR_COR_ADV_NFAT 0x00002000 653 #define PCI_ERR_COR_INTERNAL 0x00004000 654 #define PCI_ERR_COR_LOG_OVER 0x00008000 655 #define PCI_ERR_COR_MASK 20 656 #define PCI_ERR_CAP 24 657 #define PCI_ERR_CAP_FEP(x) ((x) & 31) 658 #define PCI_ERR_CAP_ECRC_GENC 0x00000020 659 #define PCI_ERR_CAP_ECRC_GENE 0x00000040 660 #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 661 #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 662 #define PCI_ERR_HEADER_LOG 28 663 #define PCI_ERR_ROOT_COMMAND 44 664 #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 665 #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 666 #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 667 #define PCI_ERR_ROOT_STATUS 48 668 #define PCI_ERR_ROOT_COR_RCV 0x00000001 669 #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 670 #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 671 #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 672 #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 673 #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 674 #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 675 #define PCI_ERR_ROOT_AER_IRQ 0xf8000000 676 #define PCI_ERR_ROOT_ERR_SRC 52 677 #define PCI_VC_PORT_CAP1 4 678 #define PCI_VC_CAP1_EVCC 0x00000007 679 #define PCI_VC_CAP1_LPEVCC 0x00000070 680 #define PCI_VC_CAP1_ARB_SIZE 0x00000c00 681 #define PCI_VC_PORT_CAP2 8 682 #define PCI_VC_CAP2_32_PHASE 0x00000002 683 #define PCI_VC_CAP2_64_PHASE 0x00000004 684 #define PCI_VC_CAP2_128_PHASE 0x00000008 685 #define PCI_VC_CAP2_ARB_OFF 0xff000000 686 #define PCI_VC_PORT_CTRL 12 687 #define PCI_VC_PORT_CTRL_LOAD_TABLE 0x00000001 688 #define PCI_VC_PORT_STATUS 14 689 #define PCI_VC_PORT_STATUS_TABLE 0x00000001 690 #define PCI_VC_RES_CAP 16 691 #define PCI_VC_RES_CAP_32_PHASE 0x00000002 692 #define PCI_VC_RES_CAP_64_PHASE 0x00000004 693 #define PCI_VC_RES_CAP_128_PHASE 0x00000008 694 #define PCI_VC_RES_CAP_128_PHASE_TB 0x00000010 695 #define PCI_VC_RES_CAP_256_PHASE 0x00000020 696 #define PCI_VC_RES_CAP_ARB_OFF 0xff000000 697 #define PCI_VC_RES_CTRL 20 698 #define PCI_VC_RES_CTRL_LOAD_TABLE 0x00010000 699 #define PCI_VC_RES_CTRL_ARB_SELECT 0x000e0000 700 #define PCI_VC_RES_CTRL_ID 0x07000000 701 #define PCI_VC_RES_CTRL_ENABLE 0x80000000 702 #define PCI_VC_RES_STATUS 26 703 #define PCI_VC_RES_STATUS_TABLE 0x00000001 704 #define PCI_VC_RES_STATUS_NEGO 0x00000002 705 #define PCI_CAP_VC_BASE_SIZEOF 0x10 706 #define PCI_CAP_VC_PER_VC_SIZEOF 0x0C 707 #define PCI_PWR_DSR 4 708 #define PCI_PWR_DATA 8 709 #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) 710 #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) 711 #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) 712 #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) 713 #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) 714 #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) 715 #define PCI_PWR_CAP 12 716 #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) 717 #define PCI_EXT_CAP_PWR_SIZEOF 16 718 #define PCI_VNDR_HEADER 4 719 #define PCI_VNDR_HEADER_ID(x) ((x) & 0xffff) 720 #define PCI_VNDR_HEADER_REV(x) (((x) >> 16) & 0xf) 721 #define PCI_VNDR_HEADER_LEN(x) (((x) >> 20) & 0xfff) 722 #define HT_3BIT_CAP_MASK 0xE0 723 #define HT_CAPTYPE_SLAVE 0x00 724 #define HT_CAPTYPE_HOST 0x20 725 #define HT_5BIT_CAP_MASK 0xF8 726 #define HT_CAPTYPE_IRQ 0x80 727 #define HT_CAPTYPE_REMAPPING_40 0xA0 728 #define HT_CAPTYPE_REMAPPING_64 0xA2 729 #define HT_CAPTYPE_UNITID_CLUMP 0x90 730 #define HT_CAPTYPE_EXTCONF 0x98 731 #define HT_CAPTYPE_MSI_MAPPING 0xA8 732 #define HT_MSI_FLAGS 0x02 733 #define HT_MSI_FLAGS_ENABLE 0x1 734 #define HT_MSI_FLAGS_FIXED 0x2 735 #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL 736 #define HT_MSI_ADDR_LO 0x04 737 #define HT_MSI_ADDR_LO_MASK 0xFFF00000 738 #define HT_MSI_ADDR_HI 0x08 739 #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 740 #define HT_CAPTYPE_VCSET 0xB8 741 #define HT_CAPTYPE_ERROR_RETRY 0xC0 742 #define HT_CAPTYPE_GEN3 0xD0 743 #define HT_CAPTYPE_PM 0xE0 744 #define HT_CAP_SIZEOF_LONG 28 745 #define HT_CAP_SIZEOF_SHORT 24 746 #define PCI_ARI_CAP 0x04 747 #define PCI_ARI_CAP_MFVC 0x0001 748 #define PCI_ARI_CAP_ACS 0x0002 749 #define PCI_ARI_CAP_NFN(x) (((x) >> 8) & 0xff) 750 #define PCI_ARI_CTRL 0x06 751 #define PCI_ARI_CTRL_MFVC 0x0001 752 #define PCI_ARI_CTRL_ACS 0x0002 753 #define PCI_ARI_CTRL_FG(x) (((x) >> 4) & 7) 754 #define PCI_EXT_CAP_ARI_SIZEOF 8 755 #define PCI_ATS_CAP 0x04 756 #define PCI_ATS_CAP_QDEP(x) ((x) & 0x1f) 757 #define PCI_ATS_MAX_QDEP 32 758 #define PCI_ATS_CAP_PAGE_ALIGNED 0x0020 759 #define PCI_ATS_CTRL 0x06 760 #define PCI_ATS_CTRL_ENABLE 0x8000 761 #define PCI_ATS_CTRL_STU(x) ((x) & 0x1f) 762 #define PCI_ATS_MIN_STU 12 763 #define PCI_EXT_CAP_ATS_SIZEOF 8 764 #define PCI_PRI_CTRL 0x04 765 #define PCI_PRI_CTRL_ENABLE 0x0001 766 #define PCI_PRI_CTRL_RESET 0x0002 767 #define PCI_PRI_STATUS 0x06 768 #define PCI_PRI_STATUS_RF 0x0001 769 #define PCI_PRI_STATUS_UPRGI 0x0002 770 #define PCI_PRI_STATUS_STOPPED 0x0100 771 #define PCI_PRI_STATUS_PASID 0x8000 772 #define PCI_PRI_MAX_REQ 0x08 773 #define PCI_PRI_ALLOC_REQ 0x0c 774 #define PCI_EXT_CAP_PRI_SIZEOF 16 775 #define PCI_PASID_CAP 0x04 776 #define PCI_PASID_CAP_EXEC 0x02 777 #define PCI_PASID_CAP_PRIV 0x04 778 #define PCI_PASID_CTRL 0x06 779 #define PCI_PASID_CTRL_ENABLE 0x01 780 #define PCI_PASID_CTRL_EXEC 0x02 781 #define PCI_PASID_CTRL_PRIV 0x04 782 #define PCI_EXT_CAP_PASID_SIZEOF 8 783 #define PCI_SRIOV_CAP 0x04 784 #define PCI_SRIOV_CAP_VFM 0x00000001 785 #define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) 786 #define PCI_SRIOV_CTRL 0x08 787 #define PCI_SRIOV_CTRL_VFE 0x0001 788 #define PCI_SRIOV_CTRL_VFM 0x0002 789 #define PCI_SRIOV_CTRL_INTR 0x0004 790 #define PCI_SRIOV_CTRL_MSE 0x0008 791 #define PCI_SRIOV_CTRL_ARI 0x0010 792 #define PCI_SRIOV_STATUS 0x0a 793 #define PCI_SRIOV_STATUS_VFM 0x0001 794 #define PCI_SRIOV_INITIAL_VF 0x0c 795 #define PCI_SRIOV_TOTAL_VF 0x0e 796 #define PCI_SRIOV_NUM_VF 0x10 797 #define PCI_SRIOV_FUNC_LINK 0x12 798 #define PCI_SRIOV_VF_OFFSET 0x14 799 #define PCI_SRIOV_VF_STRIDE 0x16 800 #define PCI_SRIOV_VF_DID 0x1a 801 #define PCI_SRIOV_SUP_PGSIZE 0x1c 802 #define PCI_SRIOV_SYS_PGSIZE 0x20 803 #define PCI_SRIOV_BAR 0x24 804 #define PCI_SRIOV_NUM_BARS 6 805 #define PCI_SRIOV_VFM 0x3c 806 #define PCI_SRIOV_VFM_BIR(x) ((x) & 7) 807 #define PCI_SRIOV_VFM_OFFSET(x) ((x) & ~7) 808 #define PCI_SRIOV_VFM_UA 0x0 809 #define PCI_SRIOV_VFM_MI 0x1 810 #define PCI_SRIOV_VFM_MO 0x2 811 #define PCI_SRIOV_VFM_AV 0x3 812 #define PCI_EXT_CAP_SRIOV_SIZEOF 64 813 #define PCI_LTR_MAX_SNOOP_LAT 0x4 814 #define PCI_LTR_MAX_NOSNOOP_LAT 0x6 815 #define PCI_LTR_VALUE_MASK 0x000003ff 816 #define PCI_LTR_SCALE_MASK 0x00001c00 817 #define PCI_LTR_SCALE_SHIFT 10 818 #define PCI_EXT_CAP_LTR_SIZEOF 8 819 #define PCI_ACS_CAP 0x04 820 #define PCI_ACS_SV 0x0001 821 #define PCI_ACS_TB 0x0002 822 #define PCI_ACS_RR 0x0004 823 #define PCI_ACS_CR 0x0008 824 #define PCI_ACS_UF 0x0010 825 #define PCI_ACS_EC 0x0020 826 #define PCI_ACS_DT 0x0040 827 #define PCI_ACS_EGRESS_BITS 0x05 828 #define PCI_ACS_CTRL 0x06 829 #define PCI_ACS_EGRESS_CTL_V 0x08 830 #define PCI_VSEC_HDR 4 831 #define PCI_VSEC_HDR_LEN_SHIFT 20 832 #define PCI_SATA_REGS 4 833 #define PCI_SATA_REGS_MASK 0xF 834 #define PCI_SATA_REGS_INLINE 0xF 835 #define PCI_SATA_SIZEOF_SHORT 8 836 #define PCI_SATA_SIZEOF_LONG 16 837 #define PCI_REBAR_CAP 4 838 #define PCI_REBAR_CAP_SIZES 0x00FFFFF0 839 #define PCI_REBAR_CTRL 8 840 #define PCI_REBAR_CTRL_BAR_IDX 0x00000007 841 #define PCI_REBAR_CTRL_NBAR_MASK 0x000000E0 842 #define PCI_REBAR_CTRL_NBAR_SHIFT 5 843 #define PCI_REBAR_CTRL_BAR_SIZE 0x00001F00 844 #define PCI_REBAR_CTRL_BAR_SHIFT 8 845 #define PCI_DPA_CAP 4 846 #define PCI_DPA_CAP_SUBSTATE_MASK 0x1F 847 #define PCI_DPA_BASE_SIZEOF 16 848 #define PCI_TPH_CAP 4 849 #define PCI_TPH_CAP_LOC_MASK 0x600 850 #define PCI_TPH_LOC_NONE 0x000 851 #define PCI_TPH_LOC_CAP 0x200 852 #define PCI_TPH_LOC_MSIX 0x400 853 #define PCI_TPH_CAP_ST_MASK 0x07FF0000 854 #define PCI_TPH_CAP_ST_SHIFT 16 855 #define PCI_TPH_BASE_SIZEOF 12 856 #define PCI_EXP_DPC_CAP 4 857 #define PCI_EXP_DPC_IRQ 0x001F 858 #define PCI_EXP_DPC_CAP_RP_EXT 0x0020 859 #define PCI_EXP_DPC_CAP_POISONED_TLP 0x0040 860 #define PCI_EXP_DPC_CAP_SW_TRIGGER 0x0080 861 #define PCI_EXP_DPC_RP_PIO_LOG_SIZE 0x0F00 862 #define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 863 #define PCI_EXP_DPC_CTL 6 864 #define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 865 #define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 866 #define PCI_EXP_DPC_CTL_INT_EN 0x0008 867 #define PCI_EXP_DPC_STATUS 8 868 #define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 869 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN 0x0006 870 #define PCI_EXP_DPC_STATUS_INTERRUPT 0x0008 871 #define PCI_EXP_DPC_RP_BUSY 0x0010 872 #define PCI_EXP_DPC_STATUS_TRIGGER_RSN_EXT 0x0060 873 #define PCI_EXP_DPC_SOURCE_ID 10 874 #define PCI_EXP_DPC_RP_PIO_STATUS 0x0C 875 #define PCI_EXP_DPC_RP_PIO_MASK 0x10 876 #define PCI_EXP_DPC_RP_PIO_SEVERITY 0x14 877 #define PCI_EXP_DPC_RP_PIO_SYSERROR 0x18 878 #define PCI_EXP_DPC_RP_PIO_EXCEPTION 0x1C 879 #define PCI_EXP_DPC_RP_PIO_HEADER_LOG 0x20 880 #define PCI_EXP_DPC_RP_PIO_IMPSPEC_LOG 0x30 881 #define PCI_EXP_DPC_RP_PIO_TLPPREFIX_LOG 0x34 882 #define PCI_PTM_CAP 0x04 883 #define PCI_PTM_CAP_REQ 0x00000001 884 #define PCI_PTM_CAP_ROOT 0x00000004 885 #define PCI_PTM_GRANULARITY_MASK 0x0000FF00 886 #define PCI_PTM_CTRL 0x08 887 #define PCI_PTM_CTRL_ENABLE 0x00000001 888 #define PCI_PTM_CTRL_ROOT 0x00000002 889 #define PCI_L1SS_CAP 0x04 890 #define PCI_L1SS_CAP_PCIPM_L1_2 0x00000001 891 #define PCI_L1SS_CAP_PCIPM_L1_1 0x00000002 892 #define PCI_L1SS_CAP_ASPM_L1_2 0x00000004 893 #define PCI_L1SS_CAP_ASPM_L1_1 0x00000008 894 #define PCI_L1SS_CAP_L1_PM_SS 0x00000010 895 #define PCI_L1SS_CAP_CM_RESTORE_TIME 0x0000ff00 896 #define PCI_L1SS_CAP_P_PWR_ON_SCALE 0x00030000 897 #define PCI_L1SS_CAP_P_PWR_ON_VALUE 0x00f80000 898 #define PCI_L1SS_CTL1 0x08 899 #define PCI_L1SS_CTL1_PCIPM_L1_2 0x00000001 900 #define PCI_L1SS_CTL1_PCIPM_L1_1 0x00000002 901 #define PCI_L1SS_CTL1_ASPM_L1_2 0x00000004 902 #define PCI_L1SS_CTL1_ASPM_L1_1 0x00000008 903 #define PCI_L1SS_CTL1_L1SS_MASK 0x0000000f 904 #define PCI_L1SS_CTL1_CM_RESTORE_TIME 0x0000ff00 905 #define PCI_L1SS_CTL1_LTR_L12_TH_VALUE 0x03ff0000 906 #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 907 #define PCI_L1SS_CTL2 0x0c 908 #define PCI_DLF_CAP 0x04 909 #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 910 #define PCI_PL_16GT_LE_CTRL 0x20 911 #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F 912 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 913 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 914 #endif 915