1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ***   To edit the content of this header, modify the corresponding
11  ***   source file (e.g. under external/kernel-headers/original/) then
12  ***   run bionic/libc/kernel/tools/update_all.py
13  ***
14  ***   Any manual change here will be lost the next time this script will
15  ***   be run. You've been warned!
16  ***
17  ****************************************************************************
18  ****************************************************************************/
19 #ifndef _V3D_DRM_H_
20 #define _V3D_DRM_H_
21 #include "drm.h"
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 #define DRM_V3D_SUBMIT_CL 0x00
26 #define DRM_V3D_WAIT_BO 0x01
27 #define DRM_V3D_CREATE_BO 0x02
28 #define DRM_V3D_MMAP_BO 0x03
29 #define DRM_V3D_GET_PARAM 0x04
30 #define DRM_V3D_GET_BO_OFFSET 0x05
31 #define DRM_V3D_SUBMIT_TFU 0x06
32 #define DRM_V3D_SUBMIT_CSD 0x07
33 #define DRM_IOCTL_V3D_SUBMIT_CL DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CL, struct drm_v3d_submit_cl)
34 #define DRM_IOCTL_V3D_WAIT_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_WAIT_BO, struct drm_v3d_wait_bo)
35 #define DRM_IOCTL_V3D_CREATE_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_CREATE_BO, struct drm_v3d_create_bo)
36 #define DRM_IOCTL_V3D_MMAP_BO DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_MMAP_BO, struct drm_v3d_mmap_bo)
37 #define DRM_IOCTL_V3D_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_PARAM, struct drm_v3d_get_param)
38 #define DRM_IOCTL_V3D_GET_BO_OFFSET DRM_IOWR(DRM_COMMAND_BASE + DRM_V3D_GET_BO_OFFSET, struct drm_v3d_get_bo_offset)
39 #define DRM_IOCTL_V3D_SUBMIT_TFU DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_TFU, struct drm_v3d_submit_tfu)
40 #define DRM_IOCTL_V3D_SUBMIT_CSD DRM_IOW(DRM_COMMAND_BASE + DRM_V3D_SUBMIT_CSD, struct drm_v3d_submit_csd)
41 #define DRM_V3D_SUBMIT_CL_FLUSH_CACHE 0x01
42 struct drm_v3d_submit_cl {
43   __u32 bcl_start;
44   __u32 bcl_end;
45   __u32 rcl_start;
46   __u32 rcl_end;
47   __u32 in_sync_bcl;
48   __u32 in_sync_rcl;
49   __u32 out_sync;
50   __u32 qma;
51   __u32 qms;
52   __u32 qts;
53   __u64 bo_handles;
54   __u32 bo_handle_count;
55   __u32 flags;
56 };
57 struct drm_v3d_wait_bo {
58   __u32 handle;
59   __u32 pad;
60   __u64 timeout_ns;
61 };
62 struct drm_v3d_create_bo {
63   __u32 size;
64   __u32 flags;
65   __u32 handle;
66   __u32 offset;
67 };
68 struct drm_v3d_mmap_bo {
69   __u32 handle;
70   __u32 flags;
71   __u64 offset;
72 };
73 enum drm_v3d_param {
74   DRM_V3D_PARAM_V3D_UIFCFG,
75   DRM_V3D_PARAM_V3D_HUB_IDENT1,
76   DRM_V3D_PARAM_V3D_HUB_IDENT2,
77   DRM_V3D_PARAM_V3D_HUB_IDENT3,
78   DRM_V3D_PARAM_V3D_CORE0_IDENT0,
79   DRM_V3D_PARAM_V3D_CORE0_IDENT1,
80   DRM_V3D_PARAM_V3D_CORE0_IDENT2,
81   DRM_V3D_PARAM_SUPPORTS_TFU,
82   DRM_V3D_PARAM_SUPPORTS_CSD,
83   DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH,
84 };
85 struct drm_v3d_get_param {
86   __u32 param;
87   __u32 pad;
88   __u64 value;
89 };
90 struct drm_v3d_get_bo_offset {
91   __u32 handle;
92   __u32 offset;
93 };
94 struct drm_v3d_submit_tfu {
95   __u32 icfg;
96   __u32 iia;
97   __u32 iis;
98   __u32 ica;
99   __u32 iua;
100   __u32 ioa;
101   __u32 ios;
102   __u32 coef[4];
103   __u32 bo_handles[4];
104   __u32 in_sync;
105   __u32 out_sync;
106 };
107 struct drm_v3d_submit_csd {
108   __u32 cfg[7];
109   __u32 coef[4];
110   __u64 bo_handles;
111   __u32 bo_handle_count;
112   __u32 in_sync;
113   __u32 out_sync;
114 };
115 #ifdef __cplusplus
116 }
117 #endif
118 #endif
119