1 /****************************************************************************
2  ****************************************************************************
3  ***
4  ***   This header was automatically generated from a Linux kernel header
5  ***   of the same name, to make information necessary for userspace to
6  ***   call into the kernel available to libc.  It contains only constants,
7  ***   structures, and macros generated from the original header, and thus,
8  ***   contains no copyrightable information.
9  ***
10  ***   To edit the content of this header, modify the corresponding
11  ***   source file (e.g. under external/kernel-headers/original/) then
12  ***   run bionic/libc/kernel/tools/update_all.py
13  ***
14  ***   Any manual change here will be lost the next time this script will
15  ***   be run. You've been warned!
16  ***
17  ****************************************************************************
18  ****************************************************************************/
19 #ifndef __QEDR_USER_H__
20 #define __QEDR_USER_H__
21 #include <linux/types.h>
22 #define QEDR_ABI_VERSION (8)
23 enum qedr_alloc_ucontext_flags {
24   QEDR_ALLOC_UCTX_RESERVED = 1 << 0,
25   QEDR_ALLOC_UCTX_DB_REC = 1 << 1
26 };
27 struct qedr_alloc_ucontext_req {
28   __u32 context_flags;
29   __u32 reserved;
30 };
31 #define QEDR_LDPM_MAX_SIZE (8192)
32 #define QEDR_EDPM_TRANS_SIZE (64)
33 enum qedr_rdma_dpm_type {
34   QEDR_DPM_TYPE_NONE = 0,
35   QEDR_DPM_TYPE_ROCE_ENHANCED = 1 << 0,
36   QEDR_DPM_TYPE_ROCE_LEGACY = 1 << 1,
37   QEDR_DPM_TYPE_IWARP_LEGACY = 1 << 2,
38   QEDR_DPM_TYPE_RESERVED = 1 << 3,
39   QEDR_DPM_SIZES_SET = 1 << 4,
40 };
41 struct qedr_alloc_ucontext_resp {
42   __aligned_u64 db_pa;
43   __u32 db_size;
44   __u32 max_send_wr;
45   __u32 max_recv_wr;
46   __u32 max_srq_wr;
47   __u32 sges_per_send_wr;
48   __u32 sges_per_recv_wr;
49   __u32 sges_per_srq_wr;
50   __u32 max_cqes;
51   __u8 dpm_flags;
52   __u8 wids_enabled;
53   __u16 wid_count;
54   __u16 ldpm_limit_size;
55   __u8 edpm_trans_size;
56   __u8 reserved;
57 };
58 struct qedr_alloc_pd_ureq {
59   __aligned_u64 rsvd1;
60 };
61 struct qedr_alloc_pd_uresp {
62   __u32 pd_id;
63   __u32 reserved;
64 };
65 struct qedr_create_cq_ureq {
66   __aligned_u64 addr;
67   __aligned_u64 len;
68 };
69 struct qedr_create_cq_uresp {
70   __u32 db_offset;
71   __u16 icid;
72   __u16 reserved;
73   __aligned_u64 db_rec_addr;
74 };
75 struct qedr_create_qp_ureq {
76   __u32 qp_handle_hi;
77   __u32 qp_handle_lo;
78   __aligned_u64 sq_addr;
79   __aligned_u64 sq_len;
80   __aligned_u64 rq_addr;
81   __aligned_u64 rq_len;
82 };
83 struct qedr_create_qp_uresp {
84   __u32 qp_id;
85   __u32 atomic_supported;
86   __u32 sq_db_offset;
87   __u16 sq_icid;
88   __u32 rq_db_offset;
89   __u16 rq_icid;
90   __u32 rq_db2_offset;
91   __u32 reserved;
92   __aligned_u64 sq_db_rec_addr;
93   __aligned_u64 rq_db_rec_addr;
94 };
95 struct qedr_create_srq_ureq {
96   __aligned_u64 prod_pair_addr;
97   __aligned_u64 srq_addr;
98   __aligned_u64 srq_len;
99 };
100 struct qedr_create_srq_uresp {
101   __u16 srq_id;
102   __u16 reserved0;
103   __u32 reserved1;
104 };
105 struct qedr_user_db_rec {
106   __aligned_u64 db_data;
107 };
108 #endif
109