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Searched refs:CTRL (Results 1 – 9 of 9) sorted by relevance

/device/google/contexthub/firmware/os/platform/stm32/
Dmpu.c122 MPU->CTRL = 0x00; // disable MPU in mpuStart()
137 MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk; in mpuStart()
160 !!(MPU->CTRL & MPU_CTRL_ENABLE_Msk), in mpuShow()
161 !!(MPU->CTRL & MPU_CTRL_HFNMIENA_Msk), in mpuShow()
162 !!(MPU->CTRL & MPU_CTRL_PRIVDEFENA_Msk)); in mpuShow()
Dplatform.c297 SysTick->CTRL = 0; in platInitialize()
300 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; in platInitialize()
440 SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); in sleepClockRtcPrepare()
447 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; in sleepClockRtcWake()
461 SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk); in sleepClockTmrPrepare()
473 SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; in sleepClockTmrWake()
/device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
Dcore_cm0plus.h462 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
513 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
803 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()
Dcore_sc000.h481 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
532 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
823 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()
Dcore_cm0.h441 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
692 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()
Dcore_cm3.h612 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
763 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1063 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
1559 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()
Dcore_sc300.h592 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
743 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1043 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
1539 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()
Dcore_cm4.h652 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
803 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1103 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
1711 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()
Dcore_cm7.h833 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Regist… member
984 …__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register … member
1287 …__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register … member
2130 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | in SysTick_Config()