1  /****************************************************************************
2   ****************************************************************************
3   ***
4   ***   This header was automatically generated from a Linux kernel header
5   ***   of the same name, to make information necessary for userspace to
6   ***   call into the kernel available to libc.  It contains only constants,
7   ***   structures, and macros generated from the original header, and thus,
8   ***   contains no copyrightable information.
9   ***
10   ***   To edit the content of this header, modify the corresponding
11   ***   source file (e.g. under external/kernel-headers/original/) then
12   ***   run bionic/libc/kernel/tools/update_all.py
13   ***
14   ***   Any manual change here will be lost the next time this script will
15   ***   be run. You've been warned!
16   ***
17   ****************************************************************************
18   ****************************************************************************/
19  #ifndef _SIW_USER_H
20  #define _SIW_USER_H
21  #include <linux/types.h>
22  #define SIW_NODE_DESC_COMMON "Software iWARP stack"
23  #define SIW_ABI_VERSION 1
24  #define SIW_MAX_SGE 6
25  #define SIW_UOBJ_MAX_KEY 0x08FFFF
26  #define SIW_INVAL_UOBJ_KEY (SIW_UOBJ_MAX_KEY + 1)
27  struct siw_uresp_create_cq {
28    __u32 cq_id;
29    __u32 num_cqe;
30    __aligned_u64 cq_key;
31  };
32  struct siw_uresp_create_qp {
33    __u32 qp_id;
34    __u32 num_sqe;
35    __u32 num_rqe;
36    __u32 pad;
37    __aligned_u64 sq_key;
38    __aligned_u64 rq_key;
39  };
40  struct siw_ureq_reg_mr {
41    __u8 stag_key;
42    __u8 reserved[3];
43    __u32 pad;
44  };
45  struct siw_uresp_reg_mr {
46    __u32 stag;
47    __u32 pad;
48  };
49  struct siw_uresp_create_srq {
50    __u32 num_rqe;
51    __u32 pad;
52    __aligned_u64 srq_key;
53  };
54  struct siw_uresp_alloc_ctx {
55    __u32 dev_id;
56    __u32 pad;
57  };
58  enum siw_opcode {
59    SIW_OP_WRITE,
60    SIW_OP_READ,
61    SIW_OP_READ_LOCAL_INV,
62    SIW_OP_SEND,
63    SIW_OP_SEND_WITH_IMM,
64    SIW_OP_SEND_REMOTE_INV,
65    SIW_OP_FETCH_AND_ADD,
66    SIW_OP_COMP_AND_SWAP,
67    SIW_OP_RECEIVE,
68    SIW_OP_READ_RESPONSE,
69    SIW_OP_INVAL_STAG,
70    SIW_OP_REG_MR,
71    SIW_NUM_OPCODES
72  };
73  struct siw_sge {
74    __aligned_u64 laddr;
75    __u32 length;
76    __u32 lkey;
77  };
78  #define SIW_MAX_INLINE (sizeof(struct siw_sge) * (SIW_MAX_SGE - 1))
79  #if SIW_MAX_SGE < 2
80  #error "SIW_MAX_SGE must be at least 2"
81  #endif
82  enum siw_wqe_flags {
83    SIW_WQE_VALID = 1,
84    SIW_WQE_INLINE = (1 << 1),
85    SIW_WQE_SIGNALLED = (1 << 2),
86    SIW_WQE_SOLICITED = (1 << 3),
87    SIW_WQE_READ_FENCE = (1 << 4),
88    SIW_WQE_REM_INVAL = (1 << 5),
89    SIW_WQE_COMPLETED = (1 << 6)
90  };
91  struct siw_sqe {
92    __aligned_u64 id;
93    __u16 flags;
94    __u8 num_sge;
95    __u8 opcode;
96    __u32 rkey;
97    union {
98      __aligned_u64 raddr;
99      __aligned_u64 base_mr;
100    };
101    union {
102      struct siw_sge sge[SIW_MAX_SGE];
103      __aligned_u64 access;
104    };
105  };
106  struct siw_rqe {
107    __aligned_u64 id;
108    __u16 flags;
109    __u8 num_sge;
110    __u8 opcode;
111    __u32 unused;
112    struct siw_sge sge[SIW_MAX_SGE];
113  };
114  enum siw_notify_flags {
115    SIW_NOTIFY_NOT = (0),
116    SIW_NOTIFY_SOLICITED = (1 << 0),
117    SIW_NOTIFY_NEXT_COMPLETION = (1 << 1),
118    SIW_NOTIFY_MISSED_EVENTS = (1 << 2),
119    SIW_NOTIFY_ALL = SIW_NOTIFY_SOLICITED | SIW_NOTIFY_NEXT_COMPLETION | SIW_NOTIFY_MISSED_EVENTS
120  };
121  enum siw_wc_status {
122    SIW_WC_SUCCESS,
123    SIW_WC_LOC_LEN_ERR,
124    SIW_WC_LOC_PROT_ERR,
125    SIW_WC_LOC_QP_OP_ERR,
126    SIW_WC_WR_FLUSH_ERR,
127    SIW_WC_BAD_RESP_ERR,
128    SIW_WC_LOC_ACCESS_ERR,
129    SIW_WC_REM_ACCESS_ERR,
130    SIW_WC_REM_INV_REQ_ERR,
131    SIW_WC_GENERAL_ERR,
132    SIW_NUM_WC_STATUS
133  };
134  struct siw_cqe {
135    __aligned_u64 id;
136    __u8 flags;
137    __u8 opcode;
138    __u16 status;
139    __u32 bytes;
140    union {
141      __aligned_u64 imm_data;
142      __u32 inval_stag;
143    };
144    union {
145      struct ib_qp * base_qp;
146      __aligned_u64 qp_id;
147    };
148  };
149  struct siw_cq_ctrl {
150    __u32 flags;
151    __u32 pad;
152  };
153  #endif
154