Lines Matching refs:shift

2136           uint32_t shift = rhs.GetImmediate() & (lhs.GetSizeInBits() - 1);  in HandleBinaryOp()  local
2137 __ Ror(dst, lhs, shift); in HandleBinaryOp()
2370 HIntConstant* shift = instruction->GetShift()->AsIntConstant(); in VisitIntermediateAddressIndex() local
2377 locations->SetInAt(1, shift->GetValue() == 0 in VisitIntermediateAddressIndex()
2380 locations->SetInAt(2, Location::ConstantLocation(shift)); in VisitIntermediateAddressIndex()
2387 uint32_t shift = Int64FromLocation(instruction->GetLocations()->InAt(2)); in VisitIntermediateAddressIndex() local
2390 if (shift == 0) { in VisitIntermediateAddressIndex()
2394 __ Add(OutputRegister(instruction), offset_reg, Operand(index_reg, LSL, shift)); in VisitIntermediateAddressIndex()
3161 int shift; in GenerateInt64DivRemWithAnyConstant() local
3162 CalculateMagicAndShiftForDivRem(imm, /* is_long= */ true, &magic, &shift); in GenerateInt64DivRemWithAnyConstant()
3189 if (shift != 0) { in GenerateInt64DivRemWithAnyConstant()
3190 __ Asr(temp, temp, shift); in GenerateInt64DivRemWithAnyConstant()
3215 int shift; in GenerateInt32DivRemWithAnyConstant() local
3216 CalculateMagicAndShiftForDivRem(imm, /* is_long= */ false, &magic, &shift); in GenerateInt32DivRemWithAnyConstant()
3244 DCHECK_LT(shift, 32); in GenerateInt32DivRemWithAnyConstant()
3248 __ Lsr(out.X(), temp.X(), 32 + shift); in GenerateInt32DivRemWithAnyConstant()
3250 __ Lsr(temp.X(), temp.X(), 32 + shift); in GenerateInt32DivRemWithAnyConstant()
3254 __ Asr(temp.X(), temp.X(), 32 + shift); in GenerateInt32DivRemWithAnyConstant()
6663 size_t shift = ComponentSizeShiftWidth(size); in VecNeonAddress() local
6669 offset += Int64FromLocation(index) << shift; in VecNeonAddress()
6673 __ Add(*scratch, base, Operand(WRegisterFrom(index), LSL, shift)); in VecNeonAddress()