Lines Matching refs:HInstruction
81 inline vixl::aarch64::Register OutputRegister(HInstruction* instr) { in OutputRegister()
85 inline vixl::aarch64::Register InputRegisterAt(HInstruction* instr, int input_index) { in InputRegisterAt()
120 inline vixl::aarch64::VRegister OutputFPRegister(HInstruction* instr) { in OutputFPRegister()
124 inline vixl::aarch64::VRegister InputFPRegisterAt(HInstruction* instr, int input_index) { in InputFPRegisterAt()
135 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) { in OutputCPURegister()
141 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) { in InputCPURegisterAt()
147 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr, in InputCPURegisterOrZeroRegAt()
149 HInstruction* input = instr->InputAt(index); in InputCPURegisterOrZeroRegAt()
171 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
241 inline bool Arm64CanEncodeConstantAsImmediate(HConstant* constant, HInstruction* instr) { in Arm64CanEncodeConstantAsImmediate()
300 inline Location ARM64EncodableConstantOrRegister(HInstruction* constant, in ARM64EncodableConstantOrRegister()
301 HInstruction* instr) { in ARM64EncodableConstantOrRegister()
359 inline bool ShifterOperandSupportsExtension(HInstruction* instruction) { in ShifterOperandSupportsExtension()
370 inline bool IsConstantZeroBitPattern(const HInstruction* instruction) { in IsConstantZeroBitPattern()