Lines Matching refs:i8
26 declare <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
30 declare <8 x i8> @llvm.aarch64.neon.sqshrun.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
366 define signext i8 @_Z3maxcc(i8 signext %v1, i8 signext %v2) nounwind readnone {
367 %1 = icmp sgt i8 %v1, %v2
368 %2 = select i1 %1, i8 %v1, i8 %v2
369 ret i8 %2
372 define <2 x i8> @_Z3maxDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
373 %1 = sext <2 x i8> %v1 to <2 x i32>
374 %2 = sext <2 x i8> %v2 to <2 x i32>
376 %4 = trunc <2 x i32> %3 to <2 x i8>
377 ret <2 x i8> %4
380 define <3 x i8> @_Z3maxDv3_cS_(i32 %v1, i32 %v2) nounwind readnone {
381 %1 = bitcast i32 %v1 to <4 x i8>
382 %2 = bitcast i32 %v2 to <4 x i8>
383 %3 = sext <4 x i8> %1 to <4 x i32>
384 %4 = sext <4 x i8> %2 to <4 x i32>
387 %7 = trunc <3 x i32> %6 to <3 x i8>
388 ret <3 x i8> %7
391 define <4 x i8> @_Z3maxDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
392 %1 = sext <4 x i8> %v1 to <4 x i32>
393 %2 = sext <4 x i8> %v2 to <4 x i32>
395 %4 = trunc <4 x i32> %3 to <4 x i8>
396 ret <4 x i8> %4
464 define zeroext i8 @_Z3maxhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
465 %1 = icmp ugt i8 %v1, %v2
466 %2 = select i1 %1, i8 %v1, i8 %v2
467 ret i8 %2
470 define <2 x i8> @_Z3maxDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
471 %1 = zext <2 x i8> %v1 to <2 x i32>
472 %2 = zext <2 x i8> %v2 to <2 x i32>
474 %4 = trunc <2 x i32> %3 to <2 x i8>
475 ret <2 x i8> %4
478 define <3 x i8> @_Z3maxDv3_hS_(i32 %v1, i32 %v2) nounwind readnone {
479 %1 = bitcast i32 %v1 to <4 x i8>
480 %2 = bitcast i32 %v2 to <4 x i8>
481 %3 = zext <4 x i8> %1 to <4 x i32>
482 %4 = zext <4 x i8> %2 to <4 x i32>
485 %7 = trunc <3 x i32> %6 to <3 x i8>
486 ret <3 x i8> %7
489 define <4 x i8> @_Z3maxDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
490 %1 = zext <4 x i8> %v1 to <4 x i32>
491 %2 = zext <4 x i8> %v2 to <4 x i32>
493 %4 = trunc <4 x i32> %3 to <4 x i8>
494 ret <4 x i8> %4
597 define signext i8 @_Z3mincc(i8 signext %v1, i8 signext %v2) nounwind readnone {
598 %1 = icmp slt i8 %v1, %v2
599 %2 = select i1 %1, i8 %v1, i8 %v2
600 ret i8 %2
603 define <2 x i8> @_Z3minDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
604 %1 = sext <2 x i8> %v1 to <2 x i32>
605 %2 = sext <2 x i8> %v2 to <2 x i32>
607 %4 = trunc <2 x i32> %3 to <2 x i8>
608 ret <2 x i8> %4
611 define <3 x i8> @_Z3minDv3_cS_(i32 %v1, i32 %v2) nounwind readnone {
612 %1 = bitcast i32 %v1 to <4 x i8>
613 %2 = bitcast i32 %v2 to <4 x i8>
614 %3 = sext <4 x i8> %1 to <4 x i32>
615 %4 = sext <4 x i8> %2 to <4 x i32>
618 %7 = trunc <3 x i32> %6 to <3 x i8>
619 ret <3 x i8> %7
622 define <4 x i8> @_Z3minDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
623 %1 = sext <4 x i8> %v1 to <4 x i32>
624 %2 = sext <4 x i8> %v2 to <4 x i32>
626 %4 = trunc <4 x i32> %3 to <4 x i8>
627 ret <4 x i8> %4
695 define zeroext i8 @_Z3minhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
696 %1 = icmp ult i8 %v1, %v2
697 %2 = select i1 %1, i8 %v1, i8 %v2
698 ret i8 %2
701 define <2 x i8> @_Z3minDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
702 %1 = zext <2 x i8> %v1 to <2 x i32>
703 %2 = zext <2 x i8> %v2 to <2 x i32>
705 %4 = trunc <2 x i32> %3 to <2 x i8>
706 ret <2 x i8> %4
709 define <3 x i8> @_Z3minDv3_hS_(i32 %v1, i32 %v2) nounwind readnone {
710 %1 = bitcast i32 %v1 to <4 x i8>
711 %2 = bitcast i32 %v2 to <4 x i8>
712 %3 = zext <4 x i8> %1 to <4 x i32>
713 %4 = zext <4 x i8> %2 to <4 x i32>
716 %7 = trunc <3 x i32> %6 to <3 x i8>
717 ret <3 x i8> %7
720 define <4 x i8> @_Z3minDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
721 %1 = zext <4 x i8> %v1 to <4 x i32>
722 %2 = zext <4 x i8> %v2 to <4 x i32>
724 %4 = trunc <4 x i32> %3 to <4 x i8>
725 ret <4 x i8> %4
834 define <4 x i8> @_Z18rsYuvToRGBA_uchar4hhh(i8 %pY, i8 %pU, i8 %pV) nounwind readnone alwaysinline {
835 %_sy = zext i8 %pY to i32
836 %_su = zext i8 %pU to i32
837 %_sv = zext i8 %pV to i32
855 ; %r2 = trunc <4 x i16> %r1 to <4 x i8>
856 ; ret <4 x i8> %r2
863 %r4 = trunc <4 x i32> %r3 to <4 x i8>
864 ret <4 x i8> %r4
968 ; %ym = call <4 x float> @llvm.aarch64.neon.ld4.v4f32(i8* %py2, i32 4) nounwind
973 ; %zm2 = call <4 x float> @llvm.aarch64.neon.ld4.v4f32(i8* %pz2, i32 4) nounwind
1103 declare <4 x i8> @_Z14convert_uchar4Dv4_f(<4 x float> %in) nounwind readnone
1104 declare <4 x float> @_Z14convert_float4Dv4_h(<4 x i8> %in) nounwind readnone
1107 define <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %color) nounwind readnone {
1114 %v4 = tail call <4 x i8> @_Z14convert_uchar4Dv4_f(<4 x float> %v3) nounwind readnone
1115 ret <4 x i8> %v4
1119 define <4 x i8> @_Z17rsPackColorTo8888Dv3_f(<4 x i32> %color) nounwind readnone {
1122 %3 = tail call <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %2) nounwind readnone
1123 ret <4 x i8> %3
1127 define <4 x i8> @_Z17rsPackColorTo8888fff(float %r, float %g, float %b) nounwind readnone {
1132 %5 = tail call <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %4) nounwind readnone
1133 ret <4 x i8> %5
1137 define <4 x i8> @_Z17rsPackColorTo8888ffff(float %r, float %g, float %b, float %a) nounwind readnon…
1142 %5 = tail call <4 x i8> @_Z17rsPackColorTo8888Dv4_f(<4 x float> %4) nounwind readnone
1143 ret <4 x i8> %5