Lines Matching refs:v1
268 define <4 x float> @_Z4fmaxDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readonly {
269 …%1 = tail call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %v1, <4 x float> %v2) nounwin…
273 define <4 x float> @_Z4fmaxDv4_ff(<4 x float> %v1, float %v2) nounwind readonly {
275 …%2 = tail call <4 x float> @llvm.aarch64.neon.fmax.v4f32(<4 x float> %v1, <4 x float> %1) nounwind…
279 define <3 x float> @_Z4fmaxDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readonly {
280 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
287 define <3 x float> @_Z4fmaxDv3_ff(<3 x float> %v1, float %v2) nounwind readonly {
288 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
295 define <2 x float> @_Z4fmaxDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readonly {
296 …%1 = tail call <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float> %v1, <2 x float> %v2) nounwin…
300 define <2 x float> @_Z4fmaxDv2_ff(<2 x float> %v1, float %v2) nounwind readonly {
302 …%2 = tail call <2 x float> @llvm.aarch64.neon.fmax.v2f32(<2 x float> %v1, <2 x float> %1) nounwind…
306 define float @_Z4fmaxff(float %v1, float %v2) nounwind readonly {
307 %1 = fcmp ogt float %v1, %v2
308 %2 = select i1 %1, float %v1, float %v2
317 define <4 x float> @_Z4fminDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readonly {
318 …%1 = tail call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %v1, <4 x float> %v2) nounwin…
322 define <4 x float> @_Z4fminDv4_ff(<4 x float> %v1, float %v2) nounwind readonly {
324 …%2 = tail call <4 x float> @llvm.aarch64.neon.fmin.v4f32(<4 x float> %v1, <4 x float> %1) nounwind…
328 define <3 x float> @_Z4fminDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readonly {
329 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
336 define <3 x float> @_Z4fminDv3_ff(<3 x float> %v1, float %v2) nounwind readonly {
337 %1 = shufflevector <3 x float> %v1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
344 define <2 x float> @_Z4fminDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readonly {
345 …%1 = tail call <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float> %v1, <2 x float> %v2) nounwin…
349 define <2 x float> @_Z4fminDv2_ff(<2 x float> %v1, float %v2) nounwind readonly {
351 …%2 = tail call <2 x float> @llvm.aarch64.neon.fmin.v2f32(<2 x float> %v1, <2 x float> %1) nounwind…
355 define float @_Z4fminff(float %v1, float %v2) nounwind readnone {
356 %1 = fcmp olt float %v1, %v2
357 %2 = select i1 %1, float %v1, float %v2
366 define signext i8 @_Z3maxcc(i8 signext %v1, i8 signext %v2) nounwind readnone {
367 %1 = icmp sgt i8 %v1, %v2
368 %2 = select i1 %1, i8 %v1, i8 %v2
372 define <2 x i8> @_Z3maxDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
373 %1 = sext <2 x i8> %v1 to <2 x i32>
380 define <3 x i8> @_Z3maxDv3_cS_(i32 %v1, i32 %v2) nounwind readnone {
381 %1 = bitcast i32 %v1 to <4 x i8>
391 define <4 x i8> @_Z3maxDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
392 %1 = sext <4 x i8> %v1 to <4 x i32>
399 define signext i16 @_Z3maxss(i16 signext %v1, i16 signext %v2) nounwind readnone {
400 %1 = icmp sgt i16 %v1, %v2
401 %2 = select i1 %1, i16 %v1, i16 %v2
405 define <2 x i16> @_Z3maxDv2_sS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
406 %1 = sext <2 x i16> %v1 to <2 x i32>
413 define <3 x i16> @_Z3maxDv3_sS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
414 %1 = sext <3 x i16> %v1 to <3 x i32>
424 define <4 x i16> @_Z3maxDv4_sS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
425 %1 = sext <4 x i16> %v1 to <4 x i32>
432 define i32 @_Z3maxii(i32 %v1, i32 %v2) nounwind readnone {
433 %1 = icmp sgt i32 %v1, %v2
434 %2 = select i1 %1, i32 %v1, i32 %v2
438 define <2 x i32> @_Z3maxDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
439 …%1 = tail call <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
443 define <3 x i32> @_Z3maxDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
444 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
451 define <4 x i32> @_Z3maxDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
452 …%1 = tail call <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
456 define i64 @_Z3maxxx(i64 %v1, i64 %v2) nounwind readnone {
457 %1 = icmp sgt i64 %v1, %v2
458 %2 = select i1 %1, i64 %v1, i64 %v2
464 define zeroext i8 @_Z3maxhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
465 %1 = icmp ugt i8 %v1, %v2
466 %2 = select i1 %1, i8 %v1, i8 %v2
470 define <2 x i8> @_Z3maxDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
471 %1 = zext <2 x i8> %v1 to <2 x i32>
478 define <3 x i8> @_Z3maxDv3_hS_(i32 %v1, i32 %v2) nounwind readnone {
479 %1 = bitcast i32 %v1 to <4 x i8>
489 define <4 x i8> @_Z3maxDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
490 %1 = zext <4 x i8> %v1 to <4 x i32>
497 define zeroext i16 @_Z3maxtt(i16 zeroext %v1, i16 zeroext %v2) nounwind readnone {
498 %1 = icmp ugt i16 %v1, %v2
499 %2 = select i1 %1, i16 %v1, i16 %v2
503 define <2 x i16> @_Z3maxDv2_tS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
504 %1 = zext <2 x i16> %v1 to <2 x i32>
511 define <3 x i16> @_Z3maxDv3_tS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
512 %1 = zext <3 x i16> %v1 to <3 x i32>
522 define <4 x i16> @_Z3maxDv4_tS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
523 %1 = zext <4 x i16> %v1 to <4 x i32>
530 define i32 @_Z3maxjj(i32 %v1, i32 %v2) nounwind readnone {
531 %1 = icmp ugt i32 %v1, %v2
532 %2 = select i1 %1, i32 %v1, i32 %v2
536 define <2 x i32> @_Z3maxDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
537 …%1 = tail call <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
541 define <3 x i32> @_Z3maxDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
542 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
549 define <4 x i32> @_Z3maxDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
550 …%1 = tail call <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
557 define float @_Z3maxff(float %v1, float %v2) nounwind readnone {
558 %1 = tail call float @_Z4fmaxff(float %v1, float %v2)
562 define <2 x float> @_Z3maxDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readnone {
563 %1 = tail call <2 x float> @_Z4fmaxDv2_fS_(<2 x float> %v1, <2 x float> %v2)
567 define <2 x float> @_Z3maxDv2_ff(<2 x float> %v1, float %v2) nounwind readnone {
568 %1 = tail call <2 x float> @_Z4fmaxDv2_ff(<2 x float> %v1, float %v2)
572 define <3 x float> @_Z3maxDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readnone {
573 %1 = tail call <3 x float> @_Z4fmaxDv3_fS_(<3 x float> %v1, <3 x float> %v2)
577 define <3 x float> @_Z3maxDv3_ff(<3 x float> %v1, float %v2) nounwind readnone {
578 %1 = tail call <3 x float> @_Z4fmaxDv3_ff(<3 x float> %v1, float %v2)
582 define <4 x float> @_Z3maxDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readnone {
583 %1 = tail call <4 x float> @_Z4fmaxDv4_fS_(<4 x float> %v1, <4 x float> %v2)
587 define <4 x float> @_Z3maxDv4_ff(<4 x float> %v1, float %v2) nounwind readnone {
588 %1 = tail call <4 x float> @_Z4fmaxDv4_ff(<4 x float> %v1, float %v2)
597 define signext i8 @_Z3mincc(i8 signext %v1, i8 signext %v2) nounwind readnone {
598 %1 = icmp slt i8 %v1, %v2
599 %2 = select i1 %1, i8 %v1, i8 %v2
603 define <2 x i8> @_Z3minDv2_cS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
604 %1 = sext <2 x i8> %v1 to <2 x i32>
611 define <3 x i8> @_Z3minDv3_cS_(i32 %v1, i32 %v2) nounwind readnone {
612 %1 = bitcast i32 %v1 to <4 x i8>
622 define <4 x i8> @_Z3minDv4_cS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
623 %1 = sext <4 x i8> %v1 to <4 x i32>
630 define signext i16 @_Z3minss(i16 signext %v1, i16 signext %v2) nounwind readnone {
631 %1 = icmp slt i16 %v1, %v2
632 %2 = select i1 %1, i16 %v1, i16 %v2
636 define <2 x i16> @_Z3minDv2_sS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
637 %1 = sext <2 x i16> %v1 to <2 x i32>
644 define <3 x i16> @_Z3minDv3_sS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
645 %1 = sext <3 x i16> %v1 to <3 x i32>
655 define <4 x i16> @_Z3minDv4_sS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
656 %1 = sext <4 x i16> %v1 to <4 x i32>
663 define i32 @_Z3minii(i32 %v1, i32 %v2) nounwind readnone {
664 %1 = icmp slt i32 %v1, %v2
665 %2 = select i1 %1, i32 %v1, i32 %v2
669 define <2 x i32> @_Z3minDv2_iS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
670 …%1 = tail call <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
674 define <3 x i32> @_Z3minDv3_iS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
675 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
682 define <4 x i32> @_Z3minDv4_iS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
683 …%1 = tail call <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
687 define i64 @_Z3minxx(i64 %v1, i64 %v2) nounwind readnone {
688 %1 = icmp slt i64 %v1, %v2
689 %2 = select i1 %1, i64 %v1, i64 %v2
695 define zeroext i8 @_Z3minhh(i8 zeroext %v1, i8 zeroext %v2) nounwind readnone {
696 %1 = icmp ult i8 %v1, %v2
697 %2 = select i1 %1, i8 %v1, i8 %v2
701 define <2 x i8> @_Z3minDv2_hS_(<2 x i8> %v1, <2 x i8> %v2) nounwind readnone {
702 %1 = zext <2 x i8> %v1 to <2 x i32>
709 define <3 x i8> @_Z3minDv3_hS_(i32 %v1, i32 %v2) nounwind readnone {
710 %1 = bitcast i32 %v1 to <4 x i8>
720 define <4 x i8> @_Z3minDv4_hS_(<4 x i8> %v1, <4 x i8> %v2) nounwind readnone {
721 %1 = zext <4 x i8> %v1 to <4 x i32>
728 define zeroext i16 @_Z3mintt(i16 zeroext %v1, i16 zeroext %v2) nounwind readnone {
729 %1 = icmp ult i16 %v1, %v2
730 %2 = select i1 %1, i16 %v1, i16 %v2
734 define <2 x i16> @_Z3minDv2_tS_(<2 x i16> %v1, <2 x i16> %v2) nounwind readnone {
735 %1 = zext <2 x i16> %v1 to <2 x i32>
742 define <3 x i16> @_Z3minDv3_tS_(<3 x i16> %v1, <3 x i16> %v2) nounwind readnone {
743 %1 = zext <3 x i16> %v1 to <3 x i32>
753 define <4 x i16> @_Z3minDv4_tS_(<4 x i16> %v1, <4 x i16> %v2) nounwind readnone {
754 %1 = zext <4 x i16> %v1 to <4 x i32>
761 define i32 @_Z3minjj(i32 %v1, i32 %v2) nounwind readnone {
762 %1 = icmp ult i32 %v1, %v2
763 %2 = select i1 %1, i32 %v1, i32 %v2
767 define <2 x i32> @_Z3minDv2_jS_(<2 x i32> %v1, <2 x i32> %v2) nounwind readnone {
768 …%1 = tail call <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32> %v1, <2 x i32> %v2) nounwind read…
772 define <3 x i32> @_Z3minDv3_jS_(<3 x i32> %v1, <3 x i32> %v2) nounwind readnone {
773 %1 = shufflevector <3 x i32> %v1, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
780 define <4 x i32> @_Z3minDv4_jS_(<4 x i32> %v1, <4 x i32> %v2) nounwind readnone {
781 …%1 = tail call <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32> %v1, <4 x i32> %v2) nounwind read…
788 define float @_Z3minff(float %v1, float %v2) nounwind readnone {
789 %1 = tail call float @_Z4fminff(float %v1, float %v2)
793 define <2 x float> @_Z3minDv2_fS_(<2 x float> %v1, <2 x float> %v2) nounwind readnone {
794 %1 = tail call <2 x float> @_Z4fminDv2_fS_(<2 x float> %v1, <2 x float> %v2)
798 define <2 x float> @_Z3minDv2_ff(<2 x float> %v1, float %v2) nounwind readnone {
799 %1 = tail call <2 x float> @_Z4fminDv2_ff(<2 x float> %v1, float %v2)
803 define <3 x float> @_Z3minDv3_fS_(<3 x float> %v1, <3 x float> %v2) nounwind readnone {
804 %1 = tail call <3 x float> @_Z4fminDv3_fS_(<3 x float> %v1, <3 x float> %v2)
808 define <3 x float> @_Z3minDv3_ff(<3 x float> %v1, float %v2) nounwind readnone {
809 %1 = tail call <3 x float> @_Z4fminDv3_ff(<3 x float> %v1, float %v2)
813 define <4 x float> @_Z3minDv4_fS_(<4 x float> %v1, <4 x float> %v2) nounwind readnone {
814 %1 = tail call <4 x float> @_Z4fminDv4_fS_(<4 x float> %v1, <4 x float> %v2)
818 define <4 x float> @_Z3minDv4_ff(<4 x float> %v1, float %v2) nounwind readnone {
819 %1 = tail call <4 x float> @_Z4fminDv4_ff(<4 x float> %v1, float %v2)
1111 %v1 = fmul <4 x float> %f255, %color
1112 %v2 = fadd <4 x float> %f05, %v1