Lines Matching refs:half

657 !61 = !{!"half", !15}
658 define void @rsSetElementAtImpl_half([1 x i32] %a.coerce, half %val, i32 %x, i32 %y, i32 %z) #1 {
660   %2 = bitcast i8* %1 to half*
661   store half %val, half* %2, align 2, !tbaa !61
665 define half @rsGetElementAtImpl_half([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 {
667   %2 = bitcast i8* %1 to half*
668   %3 = load half, half* %2, align 2, !tbaa !61
669   ret half %3
673 define void @rsSetElementAtImpl_half2([1 x i32] %a.coerce, <2 x half> %val, i32 %x, i32 %y, i32 %z)…
675   %2 = bitcast i8* %1 to <2 x half>*
676   store <2 x half> %val, <2 x half>* %2, align 4, !tbaa !62
680 define <2 x half> @rsGetElementAtImpl_half2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 {
682   %2 = bitcast i8* %1 to <2 x half>*
683   %3 = load <2 x half>, <2 x half>* %2, align 4, !tbaa !62
684   ret <2 x half> %3
688 define void @rsSetElementAtImpl_half3([1 x i32] %a.coerce, <3 x half> %val, i32 %x, i32 %y, i32 %z)…
690   %2 = shufflevector <3 x half> %val, <3 x half> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef>
691   %3 = bitcast i8* %1 to <4 x half>*
692   store <4 x half> %2, <4 x half>* %3, align 8, !tbaa !63
696 define <3 x half> @rsGetElementAtImpl_half3([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #1 {
698   %2 = bitcast i8* %1 to <4 x half>*
699   %3 = load <4 x half>, <4 x half>* %2, align 8, !tbaa !63
700   %4 = shufflevector <4 x half> %3, <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
701   ret <3 x half> %4
705 define void @rsSetElementAtImpl_half4([1 x i32] %a.coerce, <4 x half> %val, i32 %x, i32 %y, i32 %z)…
707   %2 = bitcast i8* %1 to <4 x half>*
708   store <4 x half> %val, <4 x half>* %2, align 8, !tbaa !64
712 define <4 x half> @rsGetElementAtImpl_half4([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 {
714   %2 = bitcast i8* %1 to <4 x half>*
715   %3 = load <4 x half>, <4 x half>* %2, align 8, !tbaa !64
716   ret <4 x half> %3