| /art/compiler/optimizing/ |
| D | code_generator_vector_arm64_sve.cc | 366 __ Eor(dst.V16B(), dst.V16B(), src.V16B()); in VisitVecNot() local
834 __ Eor(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecXor() local
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| D | code_generator_vector_arm64_neon.cc | 366 __ Eor(dst.V16B(), dst.V16B(), src.V16B()); in VisitVecNot() local
834 __ Eor(dst.V16B(), lhs.V16B(), rhs.V16B()); // lanes do not matter in VisitVecXor() local
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| D | code_generator_arm_vixl.cc | 1090 __ Eor(out, first, second); in GenerateDataProcInstruction() local
3146 __ Eor(out, left, right); in HandleCondition() local
3149 __ Eor(out, out, 1); in HandleCondition() local
4925 __ Eor(out_reg, out_reg, mask); in VisitAbs() local
4940 __ Eor(out_reg_lo, out_reg_lo, mask); in VisitAbs() local
4941 __ Eor(out_reg_hi, out_reg_hi, mask); in VisitAbs() local
5470 __ Eor(OutputRegister(bool_not), InputRegister(bool_not), 1); in VisitBooleanNot() local
8526 __ Eor(out, first, value); in GenerateEorConst() local
8606 __ Eor(out_reg, first_reg, second_reg); in HandleBitwiseOperation() local
8624 __ Eor(out_low, first_low, second_low); in HandleBitwiseOperation() local
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| D | intrinsics_arm_vixl.cc | 1287 __ Eor(temp1, temp2, temp_reg); in GenerateStringCompareToLoop() local
2867 __ Eor(out, out, infinity); in VisitFloatIsInfinite() local
2890 __ Eor(out, out, infinity_high); in VisitDoubleIsInfinite() local
2891 __ Eor(out, out, infinity_high2); in VisitDoubleIsInfinite() local
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| D | intrinsics_arm64.cc | 1185 __ Eor(temp2, temp2, Operand(temp3)); in VisitStringCompareTo() local
1230 __ Eor(temp1, temp2, temp4); in VisitStringCompareTo() local
2772 __ Eor(out, out, infinity); in GenIsInfinite() local
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| D | code_generator_arm64.cc | 2150 __ Eor(dst, lhs, rhs); in HandleBinaryOp() local
2344 __ Eor(out, left, right_operand); in VisitDataProcWithShifterOp() local
5501 __ Eor(OutputRegister(instruction), InputRegisterAt(instruction, 0), vixl::aarch64::Operand(1)); in VisitBooleanNot() local
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