Searched refs:Asr (Results 1 – 4 of 4) sorted by relevance
| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 103 WITH_FLAGS_DONT_CARE_RD_RN_OP(Asr);
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| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 3899 __ Asr(HighRegisterFrom(out), LowRegisterFrom(out), 31); in VisitTypeConversion() local
4238 __ Asr(out, in, ctz_imm); in DivRemByPowerOfTwo() local
4289 __ Asr(out, dividend, 31); in DivRemByPowerOfTwo() local
4374 __ Asr(temp1, temp1, shift); in GenerateDivRemWithAnyConstant() local
4923 __ Asr(mask, in_reg, 31); in VisitAbs() local
4937 __ Asr(mask, in_reg_hi, 31); in VisitAbs() local
5199 __ Asr(out_reg, first_reg, out_reg); in HandleShift() local
5211 __ Asr(out_reg, first_reg, shift_value); in HandleShift() local
5267 __ Asr(o_h, high, o_h); in HandleShift() local
5296 __ Asr(o_l, high, shift_value - 32); in HandleShift() local
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| D | code_generator_arm64.cc | 2211 __ Asr(dst, lhs, shift_value); in HandleShift() local
2221 __ Asr(dst, lhs, rhs_reg); in HandleShift() local
3104 __ Asr(out, final_dividend, ctz_imm); in FOR_EACH_CONDITION_INSTRUCTION() local
3190 __ Asr(temp, temp, shift); in GenerateInt64DivRemWithAnyConstant() local
3254 __ Asr(temp.X(), temp.X(), 32 + shift); in GenerateInt32DivRemWithAnyConstant() local
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| D | intrinsics_arm_vixl.cc | 1314 __ Asr(temp3, temp3, 7u); // uncompressed ? 0xffff0000u : 0xff0000u. in GenerateStringCompareToLoop() local
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