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Searched refs:GetId (Results 1 – 25 of 33) sorted by relevance

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/art/compiler/optimizing/
Dgraph_checker.cc157 last_instruction->GetId())); in VisitBasicBlock()
174 current->GetId())); in VisitBasicBlock()
191 current->GetId())); in VisitBasicBlock()
248 try_entry.GetId())); in VisitBasicBlock()
265 stored_try_entry.GetId(), in VisitBasicBlock()
272 stored_try_entry.GetId(), in VisitBasicBlock()
274 incoming_try_entry->GetId(), in VisitBasicBlock()
282 incoming_try_entry->GetId(), in VisitBasicBlock()
298 check->GetId())); in VisitBoundsCheck()
326 try_boundary->GetId(), in VisitTryBoundary()
[all …]
Dpretty_printer.h32 PrintInt(instruction->GetId()); in PrintPreInstruction()
53 PrintInt(input->GetId()); in PrintPostInstruction()
66 PrintInt(use.GetUser()->GetId()); in PrintPostInstruction()
134 PrintInt(gota->GetId()); in VisitGoto()
Dcode_sinking.cc129 !processed_instructions.IsBitSet(instruction->GetId()) && in AddInstruction()
316 if (processed_instructions.IsBitSet(instruction->GetId())) { in SinkCodeToUncommonBranch()
328 !instructions_that_can_move.IsBitSet(user->GetId())) { in SinkCodeToUncommonBranch()
335 if (processed_instructions.IsBitSet(user->GetId()) || in SinkCodeToUncommonBranch()
364 processed_instructions.SetBit(instruction->GetId()); in SinkCodeToUncommonBranch()
369 instructions_that_can_move.SetBit(instruction->GetId()); in SinkCodeToUncommonBranch()
371 processed_instructions.SetBit(instruction->GetId()); in SinkCodeToUncommonBranch()
408 if (!instructions_that_can_move.IsBitSet(instruction->InputAt(0)->GetId())) { in SinkCodeToUncommonBranch()
Dssa_phi_elimination.cc169 visited_phis_in_cycle.SetBit(phi->GetId()); in Run()
199 if (!visited_phis_in_cycle.IsBitSet(input->GetId())) { in Run()
201 visited_phis_in_cycle.SetBit(input->GetId()); in Run()
250 if (user->IsPhi() && !visited_phis_in_cycle.IsBitSet(user->GetId())) { in Run()
Dcode_generator_vector_arm_vixl.cc164 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecCnv()
469 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecDiv()
582 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecAndNot()
814 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecMultiplyAccumulate()
858 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecDotProd()
862 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecDotProd()
1052 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1057 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1062 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1067 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
[all …]
Dgraph_visualizer.cc604 input_list.NewEntryStream() << DataType::TypeId(input->GetType()) << input->GetId(); in PrintInstruction()
623 vregs.NewEntryStream() << DataType::TypeId(insn->GetType()) << insn->GetId(); in PrintInstruction()
712 << instruction->DebugName() << instruction->GetId() << " has invalid rti " in PrintInstruction()
736 << DataType::TypeId(instruction->GetType()) << instruction->GetId() << " "; in PrintInstructions()
859 output_ << instruction->GetId() << " " << DataType::TypeId(instruction->GetType()) in VisitBasicBlock()
860 << instruction->GetId() << "[ "; in VisitBasicBlock()
862 output_ << input->GetId() << " "; in VisitBasicBlock()
Dcode_generator_x86.h191 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_X86()
225 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_X86()
520 method_address_offset_.Put(method_base->GetId(), offset); in AddMethodAddressOffset()
524 return method_address_offset_.Get(method_base->GetId()); in GetMethodAddressOffset()
Dgraph_test.cc287 ASSERT_NE(first_instruction->GetId(), -1); in TEST_F()
300 ASSERT_NE(second_instruction->GetId(), -1); in TEST_F()
Dcode_generator_vector_x86_64.cc1164 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecMultiplyAccumulate()
1173 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecSADAccumulate()
1358 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1363 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1368 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1373 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1378 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
1383 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
Dcode_generator_vector_x86.cc1191 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecMultiplyAccumulate()
1200 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecSADAccumulate()
1385 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1390 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1395 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1400 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1405 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
1410 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
Dssa_liveness_analysis.cc117 << "Instruction " << current->DebugName() << current->GetId() in RecursivelyProcessInputs()
119 << input->DebugName() << input->GetId() << " does not produce one."; in RecursivelyProcessInputs()
Dregister_allocation_resolver.cc392 << '(' << interval->GetDefinedBy()->GetId() << ')' in ConnectSiblings()
394 << '(' << safepoint_position->GetInstruction()->GetId() << ')'; in ConnectSiblings()
447 << defined_by->DebugName() << ":" << defined_by->GetId() in ConnectSplitSiblings()
Dcode_generator_vector_arm64_sve.cc780 LOG(FATAL) << "Unsupported SIMD instruction " << instruction->GetId(); in VisitVecAndNot()
785 LOG(FATAL) << "Unsupported SIMD instruction " << instruction->GetId(); in VisitVecAndNot()
1486 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1491 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1496 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1501 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1506 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
1511 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
Dcode_generator_vector_arm64_neon.cc780 LOG(FATAL) << "Unsupported SIMD instruction " << instruction->GetId(); in VisitVecAndNot()
785 LOG(FATAL) << "Unsupported SIMD instruction " << instruction->GetId(); in VisitVecAndNot()
1486 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1491 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredSetAll()
1496 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1501 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredWhile()
1506 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
1511 LOG(FATAL) << "No SIMD for " << instruction->GetId(); in VisitVecPredCondition()
Dssa_builder.cc82 << " found for phi" << phi->GetId(); in EquivalentPhisCleanup()
426 size_t id = use.GetUser()->GetHolder()->GetId(); in HasAliasInEnvironments()
Dbounds_check_elimination.cc584 if (map->find(instruction->GetId()) != map->end()) { in LookupValueRange()
585 return map->Get(instruction->GetId()); in LookupValueRange()
599 GetValueRangeMap(basic_block)->Overwrite(instruction->GetId(), range); in AssignRange()
923 if (first_index_bounds_check_map_.find(array_length->GetId()) == in VisitBoundsCheck()
928 first_index_bounds_check_map_.Put(array_length->GetId(), bounds_check); in VisitBoundsCheck()
1369 first_index_bounds_check_map_.Get(array_length->GetId())->AsBoundsCheck(); in AddCompareWithDeoptimization()
Dcode_generator_x86_64.h195 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_X86_64()
229 << " (id " << instruction->GetId() << ")"; in FOR_EACH_CONCRETE_INSTRUCTION_X86_64()
Dnodes.cc973 DCHECK_EQ(replacement->GetId(), -1); in ReplaceAndRemoveInstructionWith()
994 DCHECK_EQ(instruction->GetId(), -1); in Add()
1012 DCHECK_EQ(instruction->GetId(), -1); in InsertInstructionBefore()
1013 DCHECK_NE(cursor->GetId(), -1); in InsertInstructionBefore()
1025 DCHECK_EQ(instruction->GetId(), -1); in InsertInstructionAfter()
1026 DCHECK_NE(cursor->GetId(), -1); in InsertInstructionAfter()
1037 DCHECK_EQ(phi->GetId(), -1); in InsertPhiAfter()
1038 DCHECK_NE(cursor->GetId(), -1); in InsertPhiAfter()
3071 os << rhs.GetInstruction()->DebugName() << ' ' << rhs.GetInstruction()->GetId(); in operator <<()
/art/test/1973-jni-id-swap-pointer/src/
DMain.java34 public static long GetId(Class<?> c, String name) { in GetId() method in Main
41 long expect_ptr_id = GetId(PtrCls.class, "doNothingPtr"); in main()
50 long expect_ptr_id2 = GetId(IdxCls.class, "doNothingIdx"); in main()
57 long again_ptr_id = GetId(PtrCls.class, "doNothingPtr"); in main()
/art/test/1972-jni-id-swap-indices/src/
DMain.java36 public static long GetId(Class<?> k, String name) { in GetId() method in Main
43 long expect_ptr_id = GetId(PtrCls.class, "doNothingPtr"); in main()
52 long expect_idx_id = GetId(IdxCls.class, "doNothingIdx"); in main()
59 long again_ptr_id = GetId(PtrCls.class, "doNothingPtr"); in main()
/art/runtime/verifier/
Dregister_line-inl.h51 line_[vdst] = new_type.GetId(); in SetRegisterType()
75 line_[vdst] = new_type1.GetId(); in SetRegisterTypeWide()
76 line_[vdst + 1] = new_type2.GetId(); in SetRegisterTypeWide()
85 result_[0] = reg_types->Undefined().GetId(); in SetResultTypeToUnknown()
92 result_[0] = new_type.GetId(); in SetResultRegisterType()
93 result_[1] = verifier->GetRegTypeCache()->Undefined().GetId(); in SetResultRegisterType()
99 result_[0] = new_type1.GetId(); in SetResultRegisterTypeWide()
100 result_[1] = new_type2.GetId(); in SetResultRegisterTypeWide()
Dregister_line.cc103 line_[i] = init_type.GetId(); in MarkRefsAsInitialized()
116 uint16_t conflict_type_id = verifier->GetRegTypeCache()->Conflict().GetId(); in MarkAllRegistersAsConflicts()
123 uint16_t conflict_type_id = verifier->GetRegTypeCache()->Conflict().GetId(); in MarkAllRegistersAsConflictsExcept()
132 uint16_t conflict_type_id = verifier->GetRegTypeCache()->Conflict().GetId(); in MarkAllRegistersAsConflictsExceptWide()
161 line_[i] = verifier->GetRegTypeCache()->Conflict().GetId(); in MarkUninitRefsAsInvalid()
176 result_[0] = verifier->GetRegTypeCache()->Undefined().GetId(); in CopyResultRegister1()
193 result_[0] = verifier->GetRegTypeCache()->Undefined().GetId(); in CopyResultRegister2()
194 result_[1] = verifier->GetRegTypeCache()->Undefined().GetId(); in CopyResultRegister2()
440 line_[idx] = new_type.GetId(); in MergeRegisters()
Dreg_type_cache.cc80 DCHECK_EQ(entries_.size(), small_precise_constants_[i]->GetId()); in FillPrimitiveAndSmallConstantTypes()
410 types.SetBit(left.GetId()); in FromUnresolvedMerge()
428 types.SetBit(right.GetId()); in FromUnresolvedMerge()
492 if (unresolved_super_child_id == child.GetId()) { in FromUnresolvedSuperClass()
497 return AddEntry(new (&allocator_) UnresolvedSuperClass(child.GetId(), this, entries_.size())); in FromUnresolvedSuperClass()
Dreg_type_test.cc482 EXPECT_EQ(ref_type.GetId(), ref_type_3.GetId()); in TEST_F()
506 EXPECT_TRUE(unresolved_parts.IsBitSet(ref_type_0.GetId())); in TEST_F()
507 EXPECT_TRUE(unresolved_parts.IsBitSet(ref_type_1.GetId())); in TEST_F()
Dreg_type.h200 uint16_t GetId() const { return cache_id_; } in GetId() function
243 bool Equals(const RegType& other) const { return GetId() == other.GetId(); } in Equals()

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