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Searched refs:GetKind (Results 1 – 25 of 31) sorted by relevance

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/art/compiler/optimizing/
Dstack_map_test.cc89 ASSERT_EQ(Kind::kInStack, dex_register_map[0].GetKind()); in TEST()
90 ASSERT_EQ(Kind::kConstant, dex_register_map[1].GetKind()); in TEST()
96 ASSERT_EQ(Kind::kInStack, location0.GetKind()); in TEST()
97 ASSERT_EQ(Kind::kConstant, location1.GetKind()); in TEST()
177 ASSERT_EQ(Kind::kInStack, dex_register_map[0].GetKind()); in TEST()
178 ASSERT_EQ(Kind::kConstant, dex_register_map[1].GetKind()); in TEST()
184 ASSERT_EQ(Kind::kInStack, location0.GetKind()); in TEST()
185 ASSERT_EQ(Kind::kConstant, location1.GetKind()); in TEST()
216 ASSERT_EQ(Kind::kInRegister, dex_register_map[0].GetKind()); in TEST()
217 ASSERT_EQ(Kind::kInFpuRegister, dex_register_map[1].GetKind()); in TEST()
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Dlocations.h146 return GetKind() == kRegister; in IsRegister()
150 return GetKind() == kFpuRegister; in IsFpuRegister()
154 return GetKind() == kRegisterPair; in IsRegisterPair()
158 return GetKind() == kFpuRegisterPair; in IsFpuRegisterPair()
257 return GetKind() == kStackSlot; in IsStackSlot()
269 return GetKind() == kDoubleStackSlot; in IsDoubleStackSlot()
281 return GetKind() == kSIMDStackSlot; in IsSIMDStackSlot()
309 Kind GetKind() const { in GetKind() function
341 switch (GetKind()) { in DebugString()
368 return GetKind() == kUnallocated; in IsUnallocated()
Dstack_map_stream.cc137 CHECK_EQ(stack_map.GetKind(), static_cast<uint32_t>(kind)); in BeginStackMapEntry()
254 entry[DexRegisterInfo::kKind] = static_cast<uint32_t>(reg.GetKind()); in CreateDexRegisterMap()
256 DexRegisterInfo::PackValue(reg.GetKind(), reg.GetValue()); in CreateDexRegisterMap()
Dparallel_move_resolver.cc366 if (loc.GetKind() == kind && !IsBlockedByMoves(loc)) { in GetScratchLocation()
372 if (loc.GetKind() == kind && !IsBlockedByMoves(loc)) { in GetScratchLocation()
456 Location::Kind kind = source.GetKind(); in PerformMove()
Dinstruction_simplifier_shared.cc141 binop->GetKind(), in TryCombineMultiplyAccumulate()
220 HBitwiseNegatedRight(op->GetType(), op->GetKind(), hother, src, op->GetDexPc()); in TryMergeNegatedInput()
Dscheduler_arm.h148 switch (instruction->GetKind()) { in IsSchedulable()
Dscheduler_arm64.h144 switch (instruction->GetKind()) { in IsSchedulable()
Dnodes_shared.h206 instr_kind_(instr->GetKind()), op_kind_(op),
Dregister_allocator.cc183 message << interval->GetDefinedBy()->GetKind() << " "; in ValidateIntervals()
Dloop_analysis.cc188 switch (inst->GetKind()) { in GetMachineInstructionCount()
Dregister_allocation_resolver.cc247 switch (source.GetKind()) { in UpdateSafepointLiveRegisters()
399 if (source.GetKind() == Location::kRegister) { in ConnectSiblings()
Dinstruction_simplifier.cc725 switch (cond->GetKind()) { in GetOppositeConditionSwapOps()
747 LOG(FATAL) << "Unknown ConditionType " << cond->GetKind(); in GetOppositeConditionSwapOps()
2790 if (instruction->GetKind() == left->GetKind() && right->IsConstant()) { in TryHandleAssociativeAndCommutativeOperation()
2793 } else if (left->IsConstant() && instruction->GetKind() == right->GetKind()) { in TryHandleAssociativeAndCommutativeOperation()
Dsuperblock_cloner_test.cc183 EXPECT_EQ(orig_instr->GetKind(), copy_instr->GetKind()); in TEST_F()
Dcode_generator.cc1332 switch (location.GetKind()) { in RecordCatchBlockInfo()
1349 LOG(FATAL) << "Unexpected kind " << location.GetKind(); in RecordCatchBlockInfo()
1377 switch (location.GetKind()) { in EmitVRegInfo()
1508 LOG(FATAL) << "Unexpected kind " << location.GetKind(); in EmitVRegInfo()
Dssa_liveness_analysis.cc330 stream << ", defined_by:" << GetParent()->GetDefinedBy()->GetKind(); in DumpWithContext()
/art/runtime/
Ddex_register_location.cc27 switch (reg.GetKind()) { in operator <<()
45 return stream << "DexRegisterLocation(" << static_cast<uint32_t>(reg.GetKind()) in operator <<()
Dcheck_reference_map_visitor.h90 switch (location.GetKind()) { in CheckOptimizedMethod()
112 LOG(FATAL) << "Unexpected location kind " << location.GetKind(); in CheckOptimizedMethod()
Ddex_register_location.h49 Kind GetKind() const { return kind_; } in GetKind() function
Dstack_map.cc150 return sm.GetPackedNativePc() < packed_pc && sm.GetKind() != StackMap::Kind::Catch; in GetStackMapForNativePcOffset()
154 StackMap::Kind kind = static_cast<StackMap::Kind>((*it).GetKind()); in GetStackMapForNativePcOffset()
204 if (regs[reg + bit].GetKind() == DexRegisterLocation::Kind::kInvalid) { in DecodeDexRegisterMap()
218 if (regs[r].GetKind() == DexRegisterLocation::Kind::kInvalid) { in DecodeDexRegisterMap()
Dstack_map.h228 DexRegisterLocation::Kind kind = static_cast<DexRegisterLocation::Kind>(GetKind()); in BIT_TABLE_HEADER()
389 if (stack_map.GetDexPc() == dex_pc && stack_map.GetKind() != StackMap::Kind::Debug) { in GetStackMapForDexPc()
400 if (stack_map.GetDexPc() == dex_pc && stack_map.GetKind() == StackMap::Kind::Catch) { in GetCatchStackMapForDexPc()
409 if (stack_map.GetDexPc() == dex_pc && stack_map.GetKind() == StackMap::Kind::OSR) { in GetOsrStackMapForDexPc()
Dquick_exception_handler.cc271 DexRegisterLocation::Kind catch_location = catch_vreg_map[vreg].GetKind(); in SetCatchEnvironmentForOptimizedHandler()
279 VRegKind vreg_kind = ToVRegKind(throw_vreg_map[vreg].GetKind()); in SetCatchEnvironmentForOptimizedHandler()
486 DexRegisterLocation::Kind location = vreg_map[vreg].GetKind(); in HandleOptimizingDeoptimization()
528 LOG(FATAL) << "Unexpected location kind " << vreg_map[vreg].GetKind(); in HandleOptimizingDeoptimization()
Dstack.cc294 DexRegisterLocation::Kind location_kind = dex_register_map[vreg].GetKind(); in GetVRegFromOptimizedCode()
334 LOG(FATAL) << "Unexpected location kind " << dex_register_map[vreg].GetKind(); in GetVRegFromOptimizedCode()
342 switch (location.GetKind()) { in GetVRegFromOptimizedCode()
361 LOG(FATAL) << "Unexpected location kind " << location.GetKind(); in GetVRegFromOptimizedCode()
/art/compiler/debug/
Delf_debug_loc_writer.h207 const Kind kind = reg_loc.GetKind(); in WriteDebugLocEntry()
212 if (piece == 0 && reg_hi.GetKind() == Kind::kInStack && in WriteDebugLocEntry()
218 if (piece == 0 && reg_hi.GetKind() == Kind::kInRegisterHigh && in WriteDebugLocEntry()
224 piece == 0 && reg_hi.GetKind() == Kind::kInFpuRegister && in WriteDebugLocEntry()
231 if (piece == 0 && reg_hi.GetKind() == Kind::kInFpuRegisterHigh && in WriteDebugLocEntry()
/art/tools/veridex/
Dveridex.h66 Primitive::Type GetKind() const { return kind_; } in GetKind() function
Dresolver.cc98 existing->second->GetKind(), last_array + 1, existing->second->GetClassDef()); in GetVeriClass()

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