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Searched refs:IsFpuRegister (Results 1 – 17 of 17) sorted by relevance

/art/compiler/optimizing/
Dlocations.h149 bool IsFpuRegister() const { in IsFpuRegister() function
162 return IsRegister() || IsFpuRegister() || IsRegisterPair() || IsFpuRegisterPair(); in IsRegisterKind()
166 DCHECK(IsRegister() || IsFpuRegister()); in reg()
188 DCHECK(IsFpuRegister()); in AsFpuRegister()
455 DCHECK(loc.IsFpuRegister()); in Add()
464 DCHECK(loc.IsFpuRegister()) << loc; in Remove()
666 || input.IsFpuRegister() in IsFixedInput()
Dcommon_arm64.h91 DCHECK(location.IsFpuRegister()) << location; in DRegisterFrom()
96 DCHECK(location.IsFpuRegister()) << location; in QRegisterFrom()
101 DCHECK(location.IsFpuRegister()) << location; in VRegisterFrom()
106 DCHECK(location.IsFpuRegister()) << location; in SRegisterFrom()
111 DCHECK(location.IsFpuRegister()) << location; in HRegisterFrom()
Dlocations.cc100 if (location.IsRegister() || location.IsFpuRegister()) { in operator <<()
Dregister_allocator_linear_scan.cc133 DCHECK(location.IsRegister() || location.IsFpuRegister()); in BlockRegister()
233 if (temp.IsRegister() || temp.IsFpuRegister()) { in ProcessInstruction()
292 if (input.IsRegister() || input.IsFpuRegister()) { in ProcessInstruction()
347 if (first.IsRegister() || first.IsFpuRegister()) { in ProcessInstruction()
357 } else if (output.IsRegister() || output.IsFpuRegister()) { in ProcessInstruction()
Dcode_generator_x86_64.cc1548 } else if (source.IsFpuRegister()) { in Move()
1563 } else if (destination.IsFpuRegister()) { in Move()
1567 } else if (source.IsFpuRegister()) { in Move()
1587 } else if (source.IsFpuRegister()) { in Move()
1604 } else if (source.IsFpuRegister()) { in Move()
1722 if (right.IsFpuRegister()) { in GenerateCompareTest()
1736 if (right.IsFpuRegister()) { in GenerateCompareTest()
3243 if (in.IsFpuRegister()) { in VisitTypeConversion()
3295 if (in.IsFpuRegister()) { in VisitTypeConversion()
3409 if (second.IsFpuRegister()) { in VisitAdd()
[all …]
Dcode_generator_x86.cc1337 } else if (source.IsFpuRegister()) { in Move32()
1343 } else if (destination.IsFpuRegister()) { in Move32()
1346 } else if (source.IsFpuRegister()) { in Move32()
1356 } else if (source.IsFpuRegister()) { in Move32()
1383 } else if (source.IsFpuRegister()) { in Move64()
1395 } else if (destination.IsFpuRegister()) { in Move64()
1396 if (source.IsFpuRegister()) { in Move64()
1420 } else if (source.IsFpuRegister()) { in Move64()
1449 if (dst_type == DataType::Type::kInt64 && !src.IsConstant() && !src.IsFpuRegister()) { in MoveLocation()
1634 if (rhs.IsFpuRegister()) { in GenerateFPCompare()
[all …]
Dcommon_arm.h83 DCHECK(location.IsFpuRegister()) << location; in SRegisterFrom()
Dregister_allocator_graph_color.cc882 if (input.IsRegister() || input.IsFpuRegister()) { in CheckForFixedInputs()
907 if (out.IsRegister() || out.IsFpuRegister()) { in CheckForFixedOutput()
955 if (temp.IsRegister() || temp.IsFpuRegister()) { in CheckForTempLiveIntervals()
1062 DCHECK(location.IsRegister() || location.IsFpuRegister()); in BlockRegister()
1438 if (input.IsRegister() || input.IsFpuRegister()) { in FindCoalesceOpportunities()
Dssa_liveness_analysis.cc480 return other.IsFpuRegister(); in SameRegisterKind()
Dcode_generator_arm_vixl.cc2499 } else if (source.IsFpuRegister()) { in Move32()
2507 } else if (destination.IsFpuRegister()) { in Move32()
2510 } else if (source.IsFpuRegister()) { in Move32()
2522 } else if (source.IsFpuRegister()) { in Move32()
6783 DCHECK(value.IsFpuRegister()); in VisitArraySet()
7049 } else if (destination.IsFpuRegister()) { in EmitMove()
7064 } else if (destination.IsFpuRegister()) { in EmitMove()
7072 } else if (source.IsFpuRegister()) { in EmitMove()
7075 } else if (destination.IsFpuRegister()) { in EmitMove()
7165 if (destination.IsFpuRegister()) { in EmitMove()
[all …]
Dregister_allocation_resolver.cc501 || destination.IsFpuRegister() in IsValidDestination()
Dgraph_visualizer.cc293 } else if (location.IsFpuRegister()) { in DumpLocation()
Dcode_generator_arm64.cc1112 DCHECK(loc.IsFpuRegister()); in FreeScratchLocation()
1476 if (destination.IsRegister() || destination.IsFpuRegister()) { in MoveLocation()
1493 DCHECK((destination.IsFpuRegister() && DataType::IsFloatingPointType(dst_type)) || in MoveLocation()
1508 DCHECK(destination.IsFpuRegister()); in MoveLocation()
1515 DCHECK(source.IsFpuRegister()); in MoveLocation()
1522 DCHECK(destination.IsFpuRegister()); in MoveLocation()
1534 if (source.IsRegister() || source.IsFpuRegister()) { in MoveLocation()
1544 (source.IsFpuRegister() == DataType::IsFloatingPointType(dst_type))); in MoveLocation()
Dcode_generator.cc68 if (location.IsFpuRegister() in CheckType()
937 } else if (location.IsFpuRegister()) { in BlockIfInRegister()
Dssa_liveness_analysis.h970 && (locations->InAt(0).IsFpuRegister() in DefinitionRequiresRegister()
Dcode_generator_vector_arm64_sve.cc1544 if (source.IsFpuRegister()) { in MoveToSIMDStackSlot()
Dcode_generator_vector_arm64_neon.cc1544 if (source.IsFpuRegister()) { in MoveToSIMDStackSlot()