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Searched refs:Operand (Results 1 – 14 of 14) sorted by relevance

/art/compiler/optimizing/
Dcommon_arm64.h163 inline vixl::aarch64::Operand OperandFrom(Location location, DataType::Type type) { in OperandFrom()
165 return vixl::aarch64::Operand(RegisterFrom(location, type)); in OperandFrom()
167 return vixl::aarch64::Operand(Int64FromLocation(location)); in OperandFrom()
171 inline vixl::aarch64::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
213 inline vixl::aarch64::Operand OperandFromMemOperand( in OperandFromMemOperand()
216 return vixl::aarch64::Operand(mem_op.GetOffset()); in OperandFromMemOperand()
220 return vixl::aarch64::Operand(mem_op.GetRegisterOffset(), in OperandFromMemOperand()
224 return vixl::aarch64::Operand(mem_op.GetRegisterOffset(), in OperandFromMemOperand()
Dcommon_arm.h190 inline vixl::aarch32::Operand OperandFrom(Location location, DataType::Type type) { in OperandFrom()
192 return vixl::aarch32::Operand(RegisterFrom(location, type)); in OperandFrom()
194 return vixl::aarch32::Operand(Int32ConstantFrom(location)); in OperandFrom()
198 inline vixl::aarch32::Operand InputOperandAt(HInstruction* instr, int input_index) { in InputOperandAt()
Dintrinsics_arm64.cc409 __ Bic(dst, dst, Operand(temp, LSL, high_bit - clz_high_bit)); // Clear dst if src was 0. in GenHighestOneBit()
978 __ Add(tmp_ptr, base.X(), Operand(offset)); in EmitNativeCode()
1045 __ Add(tmp_ptr, base.X(), Operand(offset)); in GenCas()
1185 __ Eor(temp2, temp2, Operand(temp3)); in VisitStringCompareTo()
1188 __ Ands(temp3.W(), temp3.W(), Operand(1)); in VisitStringCompareTo()
1240 __ Cmp(temp0, Operand(temp1.W(), LSR, (mirror::kUseStringCompression) ? 3 : 4)); in VisitStringCompareTo()
1246 __ Bic(temp1, temp1, Operand(temp3.X(), LSL, 3u)); in VisitStringCompareTo()
1255 __ Sub(out, temp1.W(), Operand(temp2.W(), UXTB)); in VisitStringCompareTo()
1259 __ Sub(out, temp4.W(), Operand(temp2.W(), UXTH)); in VisitStringCompareTo()
1285 __ Add(temp1, temp1, Operand(value_offset)); in VisitStringCompareTo()
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Dcode_generator_arm_vixl.cc205 __ Add(base, sp, Operand::From(stack_offset)); in SaveContiguousSRegisterList()
253 __ Add(base, sp, Operand::From(stack_offset)); in RestoreContiguousSRegisterList()
1067 const Operand& second, in GenerateDataProcInstruction()
1070 const Operand in = kind == HInstruction::kAnd in GenerateDataProcInstruction()
1071 ? Operand(0) in GenerateDataProcInstruction()
1072 : Operand(first); in GenerateDataProcInstruction()
1102 const Operand& second_lo, in GenerateDataProc()
1103 const Operand& second_hi, in GenerateDataProc()
1122 static Operand GetShifterOperand(vixl32::Register rm, ShiftType shift, uint32_t shift_imm) { in GetShifterOperand()
1123 return shift_imm == 0 ? Operand(rm) : Operand(rm, shift, shift_imm); in GetShifterOperand()
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Dcode_generator_arm64.cc197 __ Add(new_base, base, Operand(spill_offset + core_spill_size)); in SaveRestoreLiveRegistersHelper()
708 __ Add(index_reg, index_reg, Operand(offset_)); in EmitNativeCode()
1139 __ Sub(counter, counter, Operand(counter, LSR, 16)); in MaybeIncrementHotness()
1753 Operand op = OperandFromMemOperand(dst); in StoreRelease()
2125 Operand rhs = InputOperandAt(instr, 1); in HandleBinaryOp()
2204 Operand rhs = InputOperandAt(instr, 1); in HandleShift()
2308 Operand right_operand(0); in VisitDataProcWithShifterOp()
2312 right_operand = Operand(right_reg, helpers::ExtendFromOpKind(op_kind)); in VisitDataProcWithShifterOp()
2314 right_operand = Operand(right_reg, in VisitDataProcWithShifterOp()
2363 Operand(InputOperandAt(instruction, 1))); in VisitIntermediateAddress()
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Dintrinsics_arm_vixl.cc91 __ Add(base, array, Operand(RegisterFrom(pos), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyBaseAddress()
113 __ Add(end, base, Operand(RegisterFrom(copy_length), vixl32::LSL, element_size_shift)); in GenSystemArrayCopyEndAddress()
592 __ Add(RegisterFrom(temp), base, Operand(offset)); in GenUnsafeGet()
1304 __ Cmp(temp0, Operand(temp1, vixl32::LSR, (mirror::kUseStringCompression ? 3 : 4))); in GenerateStringCompareToLoop()
1313 __ Bic(temp1, temp1, Operand(temp3, vixl32::LSR, 31 - 3)); // &= ~(uncompressed ? 0xfu : 0x7u) in GenerateStringCompareToLoop()
1515 __ Cmp(temp, Operand(mirror::String::GetFlaggedCount(const_string_length, is_compressed))); in VisitStringEquals()
1587 __ Add(temp1, temp1, Operand::From(sizeof(uint32_t))); in VisitStringEquals()
2175 __ Add(src, src, Operand(temp2, vixl32::LSR, 32)); in VisitSystemArrayCopy()
2625 Operand mov_src(0); in GenHighestOneBit()
2628 mov_src = Operand(temp); in GenHighestOneBit()
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Dcode_generator_vector_arm_vixl.cc920 __ Add(*scratch, base, Operand(RegisterFrom(index), ShiftType::LSL, shift)); in VecAddress()
947 __ Add(*scratch, *scratch, Operand(RegisterFrom(index), ShiftType::LSL, shift)); in VecAddressUnaligned()
/art/compiler/utils/x86/
Dassembler_x86.cc417 EmitOperand(0, Operand(dst)); in setb()
614 EmitOperand(dst, Operand(src)); in movd()
623 EmitOperand(src, Operand(dst)); in movd()
1641 EmitOperand(dst, Operand(src)); in cvtsi2ss()
1650 EmitOperand(dst, Operand(src)); in cvtsi2sd()
2921 EmitComplex(7, Operand(reg), imm); in cmpl()
2928 EmitOperand(reg0, Operand(reg1)); in cmpl()
2999 EmitOperand(0, Operand(reg)); in testl()
3025 EmitOperand(dst, Operand(src)); in andl()
3038 EmitComplex(4, Operand(dst), imm); in andl()
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Dassembler_x86.h54 class Operand : public ValueObject {
95 Operand() : length_(0), fixup_(nullptr) { } in Operand() function
138 explicit Operand(Register reg) : fixup_(nullptr) { SetModRM(3, reg); } in Operand() function
151 class Address : public Operand {
898 void EmitOperand(int rm, const Operand& operand);
901 int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
906 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
907 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
/art/compiler/utils/arm/
Dassembler_arm_vixl.h86 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
111 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
134 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add()
Dassembler_arm_vixl.cc393 ___ Add(base, sp, Operand::From(stack_offset)); in StoreRegisterList()
413 ___ Add(base, sp, Operand::From(stack_offset)); in LoadRegisterList()
/art/compiler/utils/x86_64/
Dassembler_x86_64.cc750 EmitOperand(dst.LowBits(), Operand(src)); in movd()
759 EmitOperand(src.LowBits(), Operand(dst)); in movd()
2305 EmitOperand(dst.LowBits(), Operand(src)); in cvtsi2ss()
2340 EmitOperand(dst.LowBits(), Operand(src)); in cvtsi2sd()
3891 EmitComplex(7, Operand(reg), imm); in cmpl()
3899 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpl()
3931 EmitOperand(reg0.LowBits(), Operand(reg1)); in cmpq()
3939 EmitComplex(7, Operand(reg), imm); in cmpq()
4011 EmitOperand(0, Operand(reg)); in testl()
4056 EmitOperand(dst.LowBits(), Operand(src)); in andl()
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Dassembler_x86_64.h62 class Operand : public ValueObject {
127 Operand() : rex_(0), length_(0), fixup_(nullptr) { } in Operand() function
174 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand() function
187 class Address : public Operand {
985 void EmitOperand(uint8_t rm, const Operand& operand);
988 uint8_t rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
1005 void EmitOptionalRex32(const Operand& operand);
1006 void EmitOptionalRex32(CpuRegister dst, const Operand& operand);
1007 void EmitOptionalRex32(XmmRegister dst, const Operand& operand);
1012 void EmitRex64(const Operand& operand);
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/art/compiler/utils/arm64/
Dassembler_arm64.cc164 ___ Neg(reg, Operand(reg)); in PoisonHeapReference()
170 ___ Neg(reg, Operand(reg)); in UnpoisonHeapReference()