Searched refs:fpu_spill_mask_ (Results 1 – 4 of 4) sorted by relevance
254 uint32_t GetFpuSpillMask() const { return fpu_spill_mask_; } in GetFpuSpillMask()263 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()736 return POPCOUNT(fpu_spill_mask_) * GetCalleePreservedFPWidth(); in GetFpuSpillSize()793 uint32_t fpu_spill_mask_; variable
2070 fpu_spill_mask_ = allocated_registers_.GetFloatingPointRegisters() & fpu_callee_save_mask_; in ComputeSpillMask()2075 if (fpu_spill_mask_ != 0) { in ComputeSpillMask()2076 uint32_t least_significant_bit = LeastSignificantBit(fpu_spill_mask_); in ComputeSpillMask()2077 uint32_t most_significant_bit = MostSignificantBit(fpu_spill_mask_); in ComputeSpillMask()2079 fpu_spill_mask_ |= (1 << i); in ComputeSpillMask()2199 if ((fpu_spill_mask_ == 0u || IsPowerOfTwo(fpu_spill_mask_)) && in GenerateFrameEntry()2215 if (fpu_spill_mask_ != 0u) { in GenerateFrameEntry()2216 DCHECK(IsPowerOfTwo(fpu_spill_mask_)); in GenerateFrameEntry()2217 vixl::aarch32::SRegister sreg(LeastSignificantBit(fpu_spill_mask_)); in GenerateFrameEntry()2228 if (fpu_spill_mask_ != 0) { in GenerateFrameEntry()[all …]
390 fpu_spill_mask_, in Compile()1023 fpu_spill_mask_(0), in CodeGenerator()
1296 DCHECK(ArtVixlRegCodeCoherentForRegSet(0, 0, fpu_spill_mask_, in GetFramePreservedFPRegisters()1299 fpu_spill_mask_); in GetFramePreservedFPRegisters()