| /art/runtime/interpreter/mterp/arm/ |
| D | main.S | 245 add pc, rIBASE, \reg, lsl #${handler_size_bits}
248 add pc, \base, \reg, lsl #${handler_size_bits}
255 ldr \reg, [rFP, \vreg, lsl #2]
258 str \reg, [rFP, \vreg, lsl #2]
260 str \reg, [rREFS, \vreg, lsl #2]
263 add ip, rFP, \vreg, lsl #2
267 add ip, rREFS, \vreg, lsl #2
271 str \reg, [rFP, \vreg, lsl #2]
272 str \reg, [rREFS, \vreg, lsl #2]
275 str \reg, [rREFS, \vreg, lsl #2]
[all …]
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| D | array.S | 22 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
82 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
114 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
167 add r0, r0, r1, lsl #3 @ r0<- arrayObj + index*width
198 orr r1, r0, r1, lsl #16 @ r1<- BBBBbbbb
200 add r1, rPC, r1, lsl #1 @ r1<- PC + BBBBbbbb*2 (array data off.)
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| D | control_flow.S | 78 orrs rINST, r0, r3, lsl #16 @ rINST<- AAAAaaaa
131 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
133 add r0, rPC, r0, lsl #1 @ r0<- PC + BBBBbbbb*2
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| D | other.S | 32 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb
62 mov r0, r0, lsl #16 @ r0<- BBBB0000
83 orr r0, r0, r2, lsl #16 @ r1<- BBBBbbbb
99 orr r0, r0, r1, lsl #16 @ r0<- BBBBbbbb (low word)
102 orr r1, r2, r3, lsl #16 @ r1<- HHHHhhhh (high word)
128 orr r0, r0, r2, lsl #16 @ r0<- BBBBbbbb
141 mov r1, r1, lsl #16 @ r1<- BBBB0000
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| D | floating_point.S | 354 orrs r3, r0, r1, lsl #12
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| D | object.S | 41 add r0, r0, r1, lsl #3 @ entry address within the cache
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| /art/runtime/arch/arm64/ |
| D | memcmp16_arm64.S | 52 lsl limit, limit, #1 /* Half-words to bytes. */
78 lsl limit, limit, #3 /* Bits -> bytes. */
80 lsl mask, mask, limit
112 lsl tmp1, tmp1, #3 /* Bytes beyond alignment -> bits. */
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| D | quick_entrypoints_arm64.S | 1119 str w2, [x3, x1, lsl #2] // Heap reference = 32b
1127 str w2, [x3, x1, lsl #2] // Heap reference = 32b
1150 str w2, [x3, x1, lsl #2] // Heap reference = 32b
1604 lsl \xTemp1, \xCount, \xTemp0 // Calculate data size
1624 lsl \xTemp1, \xCount, #1
1630 lsl \xTemp1, \xCount, #2
1636 lsl \xTemp1, \xCount, #3
1720 add xIP0, xIP0, x15, lsl #(POINTER_SIZE_SHIFT + 1) // Load DexCache method slot address.
2101 add x0, x0, x2, lsl #1
2227 tst wIP0, wIP0, lsl #1
[all …]
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| /art/runtime/interpreter/mterp/arm64/ |
| D | other.S | 31 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
61 lsl w0, w0, #16 // r0<- BBBB0000
82 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb
101 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
102 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
103 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
123 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb
132 lsl x0, x0, #48
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| D | control_flow.S | 80 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa
133 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
135 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2
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| D | array.S | 186 orr x1, x0, x1, lsl #16 // x1<- ssssssssBBBBbbbb
188 add x1, xPC, x1, lsl #1 // x1<- PC + ssssssssBBBBbbbb*2 (array data off.)
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| D | main.S | 240 add \reg, xIBASE, \reg, lsl #${handler_size_bits}
244 add \reg, \base, \reg, lsl #${handler_size_bits}
567 add xPC, x0, x1, lsl #1 // generate new dex_pc_ptr
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| D | object.S | 39 add x0, x0, x1, lsl #4 // entry address within the cache
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| /art/runtime/interpreter/mterp/arm64ng/ |
| D | other.S | 10 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
37 lsl w0, w0, #16 // r0<- BBBB0000
94 orr w0, w0, w1, lsl #16 // w0<- BBBBbbbb
95 orr x0, x0, x2, lsl #32 // w0<- hhhhBBBBbbbb
96 orr x0, x0, x3, lsl #48 // w0<- HHHHhhhhBBBBbbbb
116 orr x0, x0, x2, lsl #16 // x0<- ssssssssBBBBbbbb
125 lsl x0, x0, #48
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| D | control_flow.S | 78 orr wINST, w0, w1, lsl #16 // wINST<- AAAAaaaa
131 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
133 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2
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| D | array.S | 133 orr x0, x0, x1, lsl #16 // x0<- ssssssssBBBBbbbb
135 add x0, xPC, x0, lsl #1 // x0<- PC + ssssssssBBBBbbbb*2 (array data off.)
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| D | main.S | 188 add \reg, xIBASE, \reg, lsl #${handler_size_bits}
346 lsl x14, x14, #2
355 add \refs, x14, ip2, lsl #2
358 add \fp, \refs, ip, lsl #2
602 add ip2, xREFS, x3, lsl #2 // pointer to first argument in reference array
603 add ip2, ip2, x2, lsl #2 // pointer to last argument in reference array
604 add x5, xFP, x3, lsl #2 // pointer to first argument in register array
605 add x6, x5, x2, lsl #2 // pointer to last argument in register array
716 add ip, ip, ip2, lsl #32
775 add \gpr_reg64, ip, ip2, lsl #32
[all …]
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| /art/runtime/arch/arm/ |
| D | memcmp16_arm.S | 202 orr ip, ip, lr, lsl #16
207 orreq ip, ip, lr, lsl #16
212 orreq ip, ip, lr, lsl #16
217 orreq ip, ip, lr, lsl #16
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| D | quick_entrypoints_arm.S | 791 str r2, [r3, r1, lsl #2]
798 str r2, [r3, r1, lsl #2]
819 str r2, [r3, r1, lsl #2]
1330 lsl r2, r1, r3 // Calculate data size
1360 lsl r2, r1, #1
1371 lsl r2, r1, #2
1382 lsl r2, r1, #3
1474 add r4, r4, r1, lsl #(POINTER_SIZE_SHIFT + 1) // Load DexCache method slot address.
1918 add r0, r0, r2, lsl #1
2217 lsl \reg, ip, #LOCK_WORD_STATE_FORWARDING_ADDRESS_SHIFT
[all …]
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| /art/compiler/optimizing/ |
| D | code_generator_arm_vixl.cc | 5245 __ lsl(pl, o_h, low, temp); in HandleShift() local
|