| /art/disassembler/ |
| D | disassembler_arm.cc | 85 DisassemblerStream& operator<<(const MemOperand& operand) override { in operator <<() argument
88 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
89 DisassemblerStream::operator<<(operand); in operator <<()
91 if (operand.GetBaseRegister().Is(tr) && operand.IsImmediate()) { in operator <<()
93 options_->thread_offset_name_function_(os(), operand.GetOffsetImmediate()); in operator <<()
99 DisassemblerStream& operator<<(const vixl::aarch32::AlignedMemOperand& operand) override { in operator <<() argument
102 DCHECK(!operand.GetBaseRegister().Is(pc)); in operator <<()
103 return DisassemblerStream::operator<<(operand); in operator <<()
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| /art/compiler/utils/arm/ |
| D | assembler_arm_vixl.h | 86 void (func_name)(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { \
87 MacroAssembler::func_name(vixl32::DontCare, rd, rn, operand); \
111 void (func_name)(vixl32::Register rd, const vixl32::Operand& operand) { \
112 MacroAssembler::func_name(vixl32::DontCare, rd, operand); \
134 void Add(vixl32::Register rd, vixl32::Register rn, const vixl32::Operand& operand) { in Add() argument
135 if (rd.Is(rn) && operand.IsPlainRegister()) { in Add()
136 MacroAssembler::Add(rd, rn, operand); in Add()
138 MacroAssembler::Add(vixl32::DontCare, rd, rn, operand); in Add()
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| /art/test/551-checker-shifter-operand/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
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| D | Android.bp | 3 name: "art-run-test-551-checker-shifter-operand",
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| /art/test/550-checker-multiply-accumulate/ |
| D | info.txt | 1 Test the merging of instructions into the shifter operand on arm64.
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| /art/test/434-shifter-operand/ |
| D | Android.bp | 3 name: "art-run-test-434-shifter-operand",
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| /art/compiler/utils/x86_64/ |
| D | assembler_x86_64.h | 806 void shll(CpuRegister operand, CpuRegister shifter);
808 void shrl(CpuRegister operand, CpuRegister shifter);
810 void sarl(CpuRegister operand, CpuRegister shifter);
813 void shlq(CpuRegister operand, CpuRegister shifter);
815 void shrq(CpuRegister operand, CpuRegister shifter);
817 void sarq(CpuRegister operand, CpuRegister shifter);
877 void rorl(CpuRegister operand, CpuRegister shifter);
879 void roll(CpuRegister operand, CpuRegister shifter);
882 void rorq(CpuRegister operand, CpuRegister shifter);
884 void rolq(CpuRegister operand, CpuRegister shifter);
[all …]
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| D | assembler_x86_64.cc | 4530 void X86_64Assembler::shll(CpuRegister operand, CpuRegister shifter) { in shll() argument
4531 EmitGenericShift(false, 4, operand, shifter); in shll()
4535 void X86_64Assembler::shlq(CpuRegister operand, CpuRegister shifter) { in shlq() argument
4536 EmitGenericShift(true, 4, operand, shifter); in shlq()
4550 void X86_64Assembler::shrl(CpuRegister operand, CpuRegister shifter) { in shrl() argument
4551 EmitGenericShift(false, 5, operand, shifter); in shrl()
4555 void X86_64Assembler::shrq(CpuRegister operand, CpuRegister shifter) { in shrq() argument
4556 EmitGenericShift(true, 5, operand, shifter); in shrq()
4565 void X86_64Assembler::sarl(CpuRegister operand, CpuRegister shifter) { in sarl() argument
4566 EmitGenericShift(false, 7, operand, shifter); in sarl()
[all …]
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| /art/test/162-method-resolution/jasmin/ |
| D | Test5User.j | 30 dup ; Bogus operand to be swallowed by the pop in the non-exceptional path.
34 pop ; Pops the exception or the bogus operand from above.
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| /art/compiler/utils/x86/ |
| D | assembler_x86.cc | 3301 void X86Assembler::shll(Register operand, Register shifter) { in shll() argument
3302 EmitGenericShift(4, Operand(operand), shifter); in shll()
3321 void X86Assembler::shrl(Register operand, Register shifter) { in shrl() argument
3322 EmitGenericShift(5, Operand(operand), shifter); in shrl()
3341 void X86Assembler::sarl(Register operand, Register shifter) { in sarl() argument
3342 EmitGenericShift(7, Operand(operand), shifter); in sarl()
3397 void X86Assembler::roll(Register operand, Register shifter) { in roll() argument
3398 EmitGenericShift(0, Operand(operand), shifter); in roll()
3407 void X86Assembler::rorl(Register operand, Register shifter) { in rorl() argument
3408 EmitGenericShift(1, Operand(operand), shifter); in rorl()
[all …]
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| D | assembler_x86.h | 360 void rorl(Register operand, Register shifter);
362 void roll(Register operand, Register shifter);
751 void shll(Register operand, Register shifter);
755 void shrl(Register operand, Register shifter);
759 void sarl(Register operand, Register shifter);
898 void EmitOperand(int rm, const Operand& operand);
901 int rm, const Operand& operand, const Immediate& immediate, bool is_16_op = false);
906 void EmitGenericShift(int rm, const Operand& operand, const Immediate& imm);
907 void EmitGenericShift(int rm, const Operand& operand, Register shifter);
912 X86ManagedRegister operand,
[all …]
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| /art/runtime/interpreter/mterp/arm/ |
| D | arithmetic.S | 25 cmp r1, #0 @ is second operand zero?
58 cmp r1, #0 @ is second operand zero?
89 cmp r1, #0 @ is second operand zero?
125 @cmp r1, #0 @ is second operand zero?
378 cmp r1, #0 @ is second operand zero?
407 cmp r1, #0 @ is second operand zero?
437 cmp r1, #0 @ is second operand zero?
467 @cmp r1, #0 @ is second operand zero?
633 cmp r1, #0 @ is second operand zero?
665 cmp r1, #0 @ is second operand zero?
[all …]
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| /art/compiler/optimizing/ |
| D | loop_optimization.cc | 88 /*out*/ HInstruction** operand);
94 /*out*/ HInstruction** operand) { in IsSignExtensionAndGet() argument
104 *operand = instruction; in IsSignExtensionAndGet()
111 *operand = instruction; in IsSignExtensionAndGet()
124 *operand = instruction; in IsSignExtensionAndGet()
140 *operand = conv; in IsSignExtensionAndGet()
147 IsZeroExtensionAndGet(instruction->InputAt(0), type, /*out*/ operand); in IsSignExtensionAndGet()
159 /*out*/ HInstruction** operand) { in IsZeroExtensionAndGet() argument
169 *operand = instruction; in IsZeroExtensionAndGet()
176 *operand = instruction; in IsZeroExtensionAndGet()
[all …]
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| D | code_generator_arm_vixl.cc | 1731 Operand operand(0); in GenerateConditionIntegralOrNonPrimitive() local
1734 operand = Operand::From(value); in GenerateConditionIntegralOrNonPrimitive()
1737 operand = InputOperandAt(cond, 0); in GenerateConditionIntegralOrNonPrimitive()
1740 operand = InputOperandAt(cond, 1); in GenerateConditionIntegralOrNonPrimitive()
1744 __ Subs(out, in, operand); in GenerateConditionIntegralOrNonPrimitive()
1754 __ Sub(out, in, operand); in GenerateConditionIntegralOrNonPrimitive()
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| /art/ |
| D | TEST_MAPPING | 504 "name": "art-run-test-434-shifter-operand"
822 "name": "art-run-test-551-checker-shifter-operand"
|