Searched refs:w2 (Results 1 – 17 of 17) sorted by relevance
41 lsr w2, wINST, #12 // B42 GET_VREG w2, w2 // object we're operating on46 cbz w2, common_errNullObject // null object64 ubfx w2, wINST, #8, #4 // w2<- A67 SET_VREG_OBJECT w0, w2 // fp[A]<- w069 SET_VREG_WIDE x0, w2 // fp[A]<- x071 SET_VREG w0, w2 // fp[A]<- w0107 lsr w2, wINST, #12 // w2<- B110 GET_VREG w0, w2 // w0<- object we're operating on113 ubfx w2, wINST, #8, #4 // w2<- A[all …]
80 FETCH w2, 2 // w2<- BBBB (high82 orr w0, w0, w2, lsl #16 // w1<- BBBBbbbb96 FETCH w2, 3 // w2<- hhhh (high middle)143 lsr w2, wINST, #8 // w2<- AA144 GET_VREG w0, w2 // w0<- vAA (object)164 lsr w2, wINST, #8 // w2<- AA165 GET_VREG w0, w2 // w0<- vAA (object)181 GET_VREG w2, w1 // x2<- fp[B]184 SET_VREG_OBJECT w2, w0 // fp[A]<- x2186 SET_VREG w2, w0 // fp[A]<- x2[all …]
14 FETCH_B w2, 1, 0 // w2<- BB17 GET_VREG w0, w2 // w0<- vBB (array object)25 $load w2, [x0, #$data_offset] // w2<- vBB[vCC]27 SET_VREG w2, w9 // vAA<- w246 FETCH_B w2, 1, 0 // w2<- BB49 GET_VREG w0, w2 // w0<- vBB (array object)53 lsr w2, wINST, #8 // w9<- AA56 SET_VREG_OBJECT w0, w272 and w2, w0, #255 // w2<- BB74 GET_VREG w0, w2 // w0<- vBB (array object)[all …]
21 and w2, w0, #255 // w2<- BB23 GET_VREG w0, w2 // w0<- vBB81 lsr w2, wINST, #12 // w2<- B83 GET_VREG w0, w2 // w0<- vB116 and w2, w3, #255 // w2<- BB117 GET_VREG w0, w2 // w0<- vBB146 lsr w2, w0, #8 // w2<- CC148 GET_VREG_WIDE $r2, w2 // w2<- vCC177 ubfx w2, wINST, #8, #4 // w2<- A179 GET_VREG_WIDE $r0, w2 // x0<- vA[all …]
28 lsr w2, w0, #8 // w2<- CC30 GET_VREG_DOUBLE $r2, w2 // w2<- vCC63 ubfx w2, wINST, #8, #4 // w2<- A65 GET_VREG_DOUBLE $r0, w2 // x0<- vA69 SET_VREG_DOUBLE $r0, w2 // vAA<- result80 and w2, w0, #255 // w2<- BB83 GET_VREG_DOUBLE $r1, w286 GET_VREG $r1, w2265 lsr w2, w0, #8 // w2<- CC267 GET_VREG_DOUBLE d1, w2 // d1<- vCC[all …]
12 GET_VREG w2, w0 // w2<- vA14 cmp w2, w3 // compare (vA, vB)31 GET_VREG w2, w0 // w2<- vAA34 cmp w2, #0 // compare (vA, 0)154 lsr w2, wINST, #8 // r2<- AA155 GET_VREG w0, w2 // r0<- vAA203 lsr w2, wINST, #8 // w2<- AA204 GET_VREG_WIDE x0, w2 // x0<- vAA219 lsr w2, wINST, #8 // r2<- AA220 GET_VREG w1, w2 // r1<- vAA (exception object)
608 add w2, wINST, wINST // w2<- byte offset609 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST640 add w2, wINST, wINST // w2<- byte offset641 FETCH_ADVANCE_INST_RB w2 // update rPC, load wINST
89 FETCH w2, 3 // w2<- hhhh (high middle)136 lsr w2, wINST, #8 // w2<- AA137 GET_VREG w0, w2153 lsr w2, wINST, #8 // w2<- AA154 GET_VREG w0, w2166 GET_VREG w2, w1 // x2<- fp[B]169 SET_VREG_OBJECT w2, w0 // fp[A]<- x2171 SET_VREG w2, w0 // fp[A]<- x2181 GET_VREG w2, w1 // w2<- fp[BBBB]184 SET_VREG_OBJECT w2, w0 // fp[AAAA]<- w2[all …]
28 lsr w2, wINST, #12 // w2<- B30 GET_VREG w0, w2 // w0<- object we're operating on35 ubfx w2, wINST, #8, #4 // w2<- A37 SET_VREG_OBJECT w0, w2 // fp[A]<- w048 lsr w2, wINST, #12 // w2<- B50 GET_VREG w0, w2 // w0<- object we're operating on52 ubfx w2, wINST, #8, #4 // w2<- A56 SET_VREG_WIDE x0, w2 // fp[A]<- x059 SET_VREG w0, w2 // fp[A]<- w0109 lsr w2, wINST, #12 // w2<- B[all …]
8 FETCH_B w2, 1, 0 // w2<- BB11 GET_VREG w0, w2 // w0<- vBB (array object)25 $load w2, [x0, #$data_offset] // w2<- vBB[vCC]28 SET_VREG_OBJECT w2, w9 // vAA<- w234 $load w2, [x0, #$data_offset] // w2<- vBB[vCC]35 SET_VREG w2, w9 // vAA<- w264 FETCH_B w2, 1, 0 // w2<- BB67 GET_VREG w0, w2 // w0<- vBB (array object)83 GET_VREG w2, w9 // w2<- vAA90 $store w2, [x0, #$data_offset] // vBB[vCC]<- w2[all …]
12 GET_VREG w2, w0 // w2<- vA13 cmp w2, w3 // compare (vA, vB)31 GET_VREG w2, w0 // w2<- vAA33 cmp w2, #0 // compare (vA, 0)151 lsr w2, wINST, #8 // w2<- AA153 GET_VREG_WIDE x0, w2 // x0<- vAA158 GET_VREG w0, w2 // r0<- vAA188 lsr w2, wINST, #8 // r2<- AA189 GET_VREG w0, w2 // r0<- vAA (exception object)
307 add w2, wINST, wINST // w2<- byte offset308 FETCH_ADVANCE_INST_RB w2 // update xPC, load wINST313 ldrh w2, [x0, #ART_METHOD_HOTNESS_COUNT_OFFSET]315 and w2, w2, #NTERP_HOTNESS_MASK316 strh w2, [x0, #ART_METHOD_HOTNESS_COUNT_OFFSET]318 cbz w2, NterpHandleHotnessOverflow382 ldrh w2, [x0, #ART_METHOD_HOTNESS_COUNT_OFFSET]384 and w2, w2, #NTERP_HOTNESS_MASK385 strh w2, [x0, #ART_METHOD_HOTNESS_COUNT_OFFSET]387 cbz w2, 2f[all …]
80 ldr w2, [x1, #MIRROR_OBJECT_CLASS_OFFSET]139 ldr x0, [x0, w2, uxtw #3]157 FETCH w2, 1 // offset167 ldr x0, [x0, w2, uxtw #3]
390 cbz w2, 2f391 sub w2, w2, #4 // Need 65536 bytes of range.573 LOADREG x8 4 w2 .LfillRegisters697 LOADREG x8 4 w2 .LfillRegisters2897 ldaxr w2, [x4] // Acquire needed only in most common case.898 eor w3, w2, w1 // Prepare the value to store if unlocked902 tst w2, #LOCK_WORD_GC_STATE_MASK_SHIFTED_TOGGLED // Test the non-gc bits.905 stxr w2, w3, [x4]906 cbnz w2, .Lretry_lock // If the store failed, retry.912 add w3, w2, #LOCK_WORD_THIN_LOCK_COUNT_ONE // Increment the recursive lock count.[all …]
32 int w2; field in Base41 return String.format("w0: %d, w1: %d, w2: %d, w3: %d", w0, w1, w2, w3); in baseString()104 b.w2 = 3; in exercise()
146 // 0x00000038: str w2, [sp, #208]
638 EXPECT_TRUE(vixl::aarch64::w2.Is(Arm64Assembler::reg_w(W2))); in TEST()