Searched refs:AsArm (Results 1 – 6 of 6) sorted by relevance
95 if (reg.AsArm().IsCoreRegister()) { in BuildFrame()96 core_spill_mask |= 1 << reg.AsArm().AsCoreRegister(); in BuildFrame()98 fp_spill_mask |= 1 << reg.AsArm().AsSRegister(); in BuildFrame()125 CHECK(r0.Is(AsVIXLRegister(method_reg.AsArm()))); in BuildFrame()140 if (reg.AsArm().IsCoreRegister()) { in RemoveFrame()141 core_spill_mask |= 1u << reg.AsArm().AsCoreRegister(); in RemoveFrame()143 fp_spill_mask |= 1u << reg.AsArm().AsSRegister(); in RemoveFrame()219 ArmManagedRegister src = m_src.AsArm(); in Store()243 vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm()); in StoreRef()250 vixl::aarch32::Register src = AsVIXLRegister(msrc.AsArm()); in StoreRawPtr()[all …]
267 constexpr inline arm::ArmManagedRegister ManagedRegister::AsArm() const { in AsArm() function
238 vixl32::Label* AsArm() { in AsArm() function
25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST()
51 constexpr arm::ArmManagedRegister AsArm() const;
105 if (r.AsArm().IsCoreRegister()) { in CalculateCoreCalleeSpillMask()106 result |= (1u << r.AsArm().AsCoreRegister()); in CalculateCoreCalleeSpillMask()116 if (r.AsArm().IsSRegister()) { in CalculateFpCalleeSpillMask()117 result |= (1u << r.AsArm().AsSRegister()); in CalculateFpCalleeSpillMask()