1# Copyright (C) 2016 The Android Open Source Project
2#
3# Licensed under the Apache License, Version 2.0 (the "License");
4# you may not use this file except in compliance with the License.
5# You may obtain a copy of the License at
6#
7#      http://www.apache.org/licenses/LICENSE-2.0
8#
9# Unless required by applicable law or agreed to in writing, software
10# distributed under the License is distributed on an "AS IS" BASIS,
11# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12# See the License for the specific language governing permissions and
13# limitations under the License.
14
15.class public LIrreducibleLoop;
16
17.super Ljava/lang/Object;
18
19# Test case where liveness analysis produces linear order where loop blocks are
20# not adjacent. This revealed a bug in our SSA builder, where a dead loop phi would
21# be replaced by its incoming input during SsaRedundantPhiElimination.
22
23# Check that the outer loop suspend check environment only has the parameter vreg.
24## CHECK-START: int IrreducibleLoop.liveness(int) builder (after)
25## CHECK-DAG:     <<Phi:i\d+>> Phi reg:4 loop:{{B\d+}} irreducible:false
26## CHECK-DAG:     SuspendCheck env:[[_,_,_,_,<<Phi>>]] loop:{{B\d+}} irreducible:false
27
28# Check that the linear order has non-adjacent loop blocks.
29## CHECK-START: int IrreducibleLoop.liveness(int) liveness (after)
30## CHECK-DAG:     Mul liveness:<<LPreEntry2:\d+>>
31## CHECK-DAG:     Add liveness:<<LBackEdge1:\d+>>
32## CHECK-EVAL:    <<LBackEdge1>> < <<LPreEntry2>>
33
34.method public static liveness(I)I
35    .registers 5
36
37    const-string v1, "MyString"
38
39    :header1
40    if-eqz p0, :body1
41
42    :exit
43    return p0
44
45    :body1
46    # The test will generate an incorrect linear order when the following IF swaps
47    # its successors. To do that, load a boolean value and compare NotEqual to 1.
48    sget-boolean v2, LIrreducibleLoop;->f:Z
49    const v3, 1
50    if-ne v2, v3, :pre_header2
51
52    :pre_entry2
53    # Add a marker on the irreducible loop entry.
54    mul-int/2addr p0, p0
55    goto :back_edge2
56
57    :back_edge2
58    goto :header2
59
60    :header2
61    if-eqz p0, :back_edge2
62
63    :back_edge1
64    # Add a marker on the outer loop back edge.
65    add-int/2addr p0, p0
66    # Set a wide register, to have v1 undefined at the back edge.
67    const-wide/16 v0, 0x1
68    goto :header1
69
70    :pre_header2
71    goto :header2
72.end method
73
74.field public static f:Z
75